ddr.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. #include <log.h>
  9. #include <asm/arch/soc.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/global_data.h>
  12. #include "ddr.h"
  13. DECLARE_GLOBAL_DATA_PTR;
  14. void fsl_ddr_board_options(memctl_options_t *popts,
  15. dimm_params_t *pdimm,
  16. unsigned int ctrl_num)
  17. {
  18. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  19. u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
  20. #endif
  21. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  22. ulong ddr_freq;
  23. int slot;
  24. if (ctrl_num > 2) {
  25. printf("Not supported controller number %d\n", ctrl_num);
  26. return;
  27. }
  28. for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
  29. if (pdimm[slot].n_ranks)
  30. break;
  31. }
  32. if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
  33. return;
  34. /*
  35. * we use identical timing for all slots. If needed, change the code
  36. * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  37. */
  38. if (popts->registered_dimm_en)
  39. pbsp = rdimms[ctrl_num];
  40. else
  41. pbsp = udimms[ctrl_num];
  42. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  43. * freqency and n_banks specified in board_specific_parameters table.
  44. */
  45. ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
  46. while (pbsp->datarate_mhz_high) {
  47. if (pbsp->n_ranks == pdimm[slot].n_ranks &&
  48. (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
  49. if (ddr_freq <= pbsp->datarate_mhz_high) {
  50. popts->clk_adjust = pbsp->clk_adjust;
  51. popts->wrlvl_start = pbsp->wrlvl_start;
  52. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  53. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  54. goto found;
  55. }
  56. pbsp_highest = pbsp;
  57. }
  58. pbsp++;
  59. }
  60. if (pbsp_highest) {
  61. printf("Error: board specific timing not found for data rate %lu MT/s\n"
  62. "Trying to use the highest speed (%u) parameters\n",
  63. ddr_freq, pbsp_highest->datarate_mhz_high);
  64. popts->clk_adjust = pbsp_highest->clk_adjust;
  65. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  66. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  67. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  68. } else {
  69. panic("DIMM is not supported by this board");
  70. }
  71. found:
  72. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  73. "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  74. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  75. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  76. pbsp->wrlvl_ctl_3);
  77. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  78. if (ctrl_num == CONFIG_DP_DDR_CTRL) {
  79. /* force DDR bus width to 32 bits */
  80. popts->data_bus_width = 1;
  81. popts->otf_burst_chop_en = 0;
  82. popts->burst_length = DDR_BL8;
  83. popts->bstopre = 0; /* enable auto precharge */
  84. /*
  85. * Layout optimization results byte mapping
  86. * Byte 0 -> Byte ECC
  87. * Byte 1 -> Byte 3
  88. * Byte 2 -> Byte 2
  89. * Byte 3 -> Byte 1
  90. * Byte ECC -> Byte 0
  91. */
  92. dq_mapping_0 = pdimm[slot].dq_mapping[0];
  93. dq_mapping_2 = pdimm[slot].dq_mapping[2];
  94. dq_mapping_3 = pdimm[slot].dq_mapping[3];
  95. pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
  96. pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
  97. pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
  98. pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
  99. pdimm[slot].dq_mapping[6] = dq_mapping_2;
  100. pdimm[slot].dq_mapping[7] = dq_mapping_3;
  101. pdimm[slot].dq_mapping[8] = dq_mapping_0;
  102. pdimm[slot].dq_mapping[9] = 0;
  103. pdimm[slot].dq_mapping[10] = 0;
  104. pdimm[slot].dq_mapping[11] = 0;
  105. pdimm[slot].dq_mapping[12] = 0;
  106. pdimm[slot].dq_mapping[13] = 0;
  107. pdimm[slot].dq_mapping[14] = 0;
  108. pdimm[slot].dq_mapping[15] = 0;
  109. pdimm[slot].dq_mapping[16] = 0;
  110. pdimm[slot].dq_mapping[17] = 0;
  111. }
  112. #endif
  113. /* To work at higher than 1333MT/s */
  114. popts->half_strength_driver_enable = 0;
  115. /*
  116. * Write leveling override
  117. */
  118. popts->wrlvl_override = 1;
  119. popts->wrlvl_sample = 0x0; /* 32 clocks */
  120. /*
  121. * Rtt and Rtt_WR override
  122. */
  123. popts->rtt_override = 0;
  124. /* Enable ZQ calibration */
  125. popts->zq_en = 1;
  126. if (ddr_freq < 2350) {
  127. if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
  128. /* four chip-selects */
  129. popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
  130. DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  131. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
  132. popts->twot_en = 1; /* enable 2T timing */
  133. } else {
  134. popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
  135. DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
  136. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
  137. DDR_CDR2_VREF_RANGE_2;
  138. }
  139. } else {
  140. popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
  141. DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
  142. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
  143. DDR_CDR2_VREF_RANGE_2;
  144. }
  145. }
  146. #ifdef CONFIG_TFABOOT
  147. int fsl_initdram(void)
  148. {
  149. gd->ram_size = tfa_get_dram_size();
  150. if (!gd->ram_size)
  151. gd->ram_size = fsl_ddr_sdram_size();
  152. return 0;
  153. }
  154. #else
  155. int fsl_initdram(void)
  156. {
  157. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  158. gd->ram_size = fsl_ddr_sdram_size();
  159. #else
  160. puts("Initializing DDR....using SPD\n");
  161. gd->ram_size = fsl_ddr_sdram();
  162. #endif
  163. return 0;
  164. }
  165. #endif /* CONFIG_TFABOOT */