ls1088a.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2018 NXP
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <i2c.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <errno.h>
  12. #include <netdev.h>
  13. #include <fsl_ifc.h>
  14. #include <fsl_ddr.h>
  15. #include <fsl_sec.h>
  16. #include <asm/global_data.h>
  17. #include <asm/io.h>
  18. #include <fdt_support.h>
  19. #include <linux/delay.h>
  20. #include <linux/libfdt.h>
  21. #include <fsl-mc/fsl_mc.h>
  22. #include <env_internal.h>
  23. #include <asm/arch-fsl-layerscape/soc.h>
  24. #include <asm/arch/ppa.h>
  25. #include <hwconfig.h>
  26. #include <asm/arch/fsl_serdes.h>
  27. #include <asm/arch/soc.h>
  28. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  29. #include "../common/i2c_mux.h"
  30. #include "../common/qixis.h"
  31. #include "ls1088a_qixis.h"
  32. #include "../common/vid.h"
  33. #include <fsl_immap.h>
  34. DECLARE_GLOBAL_DATA_PTR;
  35. #ifdef CONFIG_TARGET_LS1088AQDS
  36. #ifdef CONFIG_TFABOOT
  37. struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  38. {
  39. "nor0",
  40. CONFIG_SYS_NOR0_CSPR_EARLY,
  41. CONFIG_SYS_NOR0_CSPR_EXT,
  42. CONFIG_SYS_NOR_AMASK,
  43. CONFIG_SYS_NOR_CSOR,
  44. {
  45. CONFIG_SYS_NOR_FTIM0,
  46. CONFIG_SYS_NOR_FTIM1,
  47. CONFIG_SYS_NOR_FTIM2,
  48. CONFIG_SYS_NOR_FTIM3
  49. },
  50. 0,
  51. CONFIG_SYS_NOR0_CSPR,
  52. 0,
  53. },
  54. {
  55. "nor1",
  56. CONFIG_SYS_NOR1_CSPR_EARLY,
  57. CONFIG_SYS_NOR0_CSPR_EXT,
  58. CONFIG_SYS_NOR_AMASK_EARLY,
  59. CONFIG_SYS_NOR_CSOR,
  60. {
  61. CONFIG_SYS_NOR_FTIM0,
  62. CONFIG_SYS_NOR_FTIM1,
  63. CONFIG_SYS_NOR_FTIM2,
  64. CONFIG_SYS_NOR_FTIM3
  65. },
  66. 0,
  67. CONFIG_SYS_NOR1_CSPR,
  68. CONFIG_SYS_NOR_AMASK,
  69. },
  70. {
  71. "nand",
  72. CONFIG_SYS_NAND_CSPR,
  73. CONFIG_SYS_NAND_CSPR_EXT,
  74. CONFIG_SYS_NAND_AMASK,
  75. CONFIG_SYS_NAND_CSOR,
  76. {
  77. CONFIG_SYS_NAND_FTIM0,
  78. CONFIG_SYS_NAND_FTIM1,
  79. CONFIG_SYS_NAND_FTIM2,
  80. CONFIG_SYS_NAND_FTIM3
  81. },
  82. },
  83. {
  84. "fpga",
  85. CONFIG_SYS_FPGA_CSPR,
  86. CONFIG_SYS_FPGA_CSPR_EXT,
  87. SYS_FPGA_AMASK,
  88. CONFIG_SYS_FPGA_CSOR,
  89. {
  90. SYS_FPGA_CS_FTIM0,
  91. SYS_FPGA_CS_FTIM1,
  92. SYS_FPGA_CS_FTIM2,
  93. SYS_FPGA_CS_FTIM3
  94. },
  95. 0,
  96. SYS_FPGA_CSPR_FINAL,
  97. 0,
  98. }
  99. };
  100. struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  101. {
  102. "nand",
  103. CONFIG_SYS_NAND_CSPR,
  104. CONFIG_SYS_NAND_CSPR_EXT,
  105. CONFIG_SYS_NAND_AMASK,
  106. CONFIG_SYS_NAND_CSOR,
  107. {
  108. CONFIG_SYS_NAND_FTIM0,
  109. CONFIG_SYS_NAND_FTIM1,
  110. CONFIG_SYS_NAND_FTIM2,
  111. CONFIG_SYS_NAND_FTIM3
  112. },
  113. },
  114. {
  115. "reserved",
  116. },
  117. {
  118. "fpga",
  119. CONFIG_SYS_FPGA_CSPR,
  120. CONFIG_SYS_FPGA_CSPR_EXT,
  121. SYS_FPGA_AMASK,
  122. CONFIG_SYS_FPGA_CSOR,
  123. {
  124. SYS_FPGA_CS_FTIM0,
  125. SYS_FPGA_CS_FTIM1,
  126. SYS_FPGA_CS_FTIM2,
  127. SYS_FPGA_CS_FTIM3
  128. },
  129. 0,
  130. SYS_FPGA_CSPR_FINAL,
  131. 0,
  132. }
  133. };
  134. void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  135. {
  136. enum boot_src src = get_boot_src();
  137. if (src == BOOT_SOURCE_QSPI_NOR)
  138. regs_info->regs = ifc_cfg_qspi_nor_boot;
  139. else
  140. regs_info->regs = ifc_cfg_ifc_nor_boot;
  141. regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  142. }
  143. #endif /* CONFIG_TFABOOT */
  144. #endif /* CONFIG_TARGET_LS1088AQDS */
  145. int board_early_init_f(void)
  146. {
  147. #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
  148. i2c_early_init_f();
  149. #endif
  150. fsl_lsch3_early_init_f();
  151. return 0;
  152. }
  153. #ifdef CONFIG_FSL_QIXIS
  154. unsigned long long get_qixis_addr(void)
  155. {
  156. unsigned long long addr;
  157. if (gd->flags & GD_FLG_RELOC)
  158. addr = QIXIS_BASE_PHYS;
  159. else
  160. addr = QIXIS_BASE_PHYS_EARLY;
  161. /*
  162. * IFC address under 256MB is mapped to 0x30000000, any address above
  163. * is mapped to 0x5_10000000 up to 4GB.
  164. */
  165. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  166. return addr;
  167. }
  168. #endif
  169. #if defined(CONFIG_VID)
  170. int init_func_vid(void)
  171. {
  172. if (adjust_vdd(0) < 0)
  173. printf("core voltage not adjusted\n");
  174. return 0;
  175. }
  176. u16 soc_get_fuse_vid(int vid_index)
  177. {
  178. static const u16 vdd[32] = {
  179. 10250,
  180. 9875,
  181. 9750,
  182. 0, /* reserved */
  183. 0, /* reserved */
  184. 0, /* reserved */
  185. 0, /* reserved */
  186. 0, /* reserved */
  187. 9000,
  188. 0, /* reserved */
  189. 0, /* reserved */
  190. 0, /* reserved */
  191. 0, /* reserved */
  192. 0, /* reserved */
  193. 0, /* reserved */
  194. 0, /* reserved */
  195. 10000, /* 1.0000V */
  196. 10125,
  197. 10250,
  198. 0, /* reserved */
  199. 0, /* reserved */
  200. 0, /* reserved */
  201. 0, /* reserved */
  202. 0, /* reserved */
  203. 0, /* reserved */
  204. 0, /* reserved */
  205. 0, /* reserved */
  206. 0, /* reserved */
  207. 0, /* reserved */
  208. 0, /* reserved */
  209. 0, /* reserved */
  210. 0, /* reserved */
  211. };
  212. return vdd[vid_index];
  213. };
  214. #endif
  215. int is_pb_board(void)
  216. {
  217. u8 board_id;
  218. board_id = QIXIS_READ(id);
  219. if (board_id == LS1088ARDB_PB_BOARD)
  220. return 1;
  221. else
  222. return 0;
  223. }
  224. int fixup_ls1088ardb_pb_banner(void *fdt)
  225. {
  226. fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
  227. return 0;
  228. }
  229. #if !defined(CONFIG_SPL_BUILD)
  230. int checkboard(void)
  231. {
  232. #ifdef CONFIG_TFABOOT
  233. enum boot_src src = get_boot_src();
  234. #endif
  235. char buf[64];
  236. u8 sw;
  237. static const char *const freq[] = {"100", "125", "156.25",
  238. "100 separate SSCG"};
  239. int clock;
  240. #ifdef CONFIG_TARGET_LS1088AQDS
  241. printf("Board: LS1088A-QDS, ");
  242. #else
  243. if (is_pb_board())
  244. printf("Board: LS1088ARDB-PB, ");
  245. else
  246. printf("Board: LS1088A-RDB, ");
  247. #endif
  248. sw = QIXIS_READ(arch);
  249. printf("Board Arch: V%d, ", sw >> 4);
  250. #ifdef CONFIG_TARGET_LS1088AQDS
  251. printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  252. #else
  253. printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  254. #endif
  255. memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
  256. sw = QIXIS_READ(brdcfg[0]);
  257. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  258. #ifdef CONFIG_TFABOOT
  259. if (src == BOOT_SOURCE_SD_MMC)
  260. puts("SD card\n");
  261. #else
  262. #ifdef CONFIG_SD_BOOT
  263. puts("SD card\n");
  264. #endif
  265. #endif /* CONFIG_TFABOOT */
  266. switch (sw) {
  267. #ifdef CONFIG_TARGET_LS1088AQDS
  268. case 0:
  269. case 1:
  270. case 2:
  271. case 3:
  272. case 4:
  273. case 5:
  274. case 6:
  275. case 7:
  276. printf("vBank: %d\n", sw);
  277. break;
  278. case 8:
  279. puts("PromJet\n");
  280. break;
  281. case 15:
  282. puts("IFCCard\n");
  283. break;
  284. case 14:
  285. #else
  286. case 0:
  287. #endif
  288. puts("QSPI:");
  289. sw = QIXIS_READ(brdcfg[0]);
  290. sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
  291. if (sw == 0 || sw == 4)
  292. puts("0\n");
  293. else if (sw == 1)
  294. puts("1\n");
  295. else
  296. puts("EMU\n");
  297. break;
  298. default:
  299. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  300. break;
  301. }
  302. #ifdef CONFIG_TARGET_LS1088AQDS
  303. printf("FPGA: v%d (%s), build %d",
  304. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  305. (int)qixis_read_minor());
  306. /* the timestamp string contains "\n" at the end */
  307. printf(" on %s", qixis_read_time(buf));
  308. #else
  309. printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  310. #endif
  311. /*
  312. * Display the actual SERDES reference clocks as configured by the
  313. * dip switches on the board. Note that the SWx registers could
  314. * technically be set to force the reference clocks to match the
  315. * values that the SERDES expects (or vice versa). For now, however,
  316. * we just display both values and hope the user notices when they
  317. * don't match.
  318. */
  319. puts("SERDES1 Reference : ");
  320. sw = QIXIS_READ(brdcfg[2]);
  321. clock = (sw >> 6) & 3;
  322. printf("Clock1 = %sMHz ", freq[clock]);
  323. clock = (sw >> 4) & 3;
  324. printf("Clock2 = %sMHz", freq[clock]);
  325. puts("\nSERDES2 Reference : ");
  326. clock = (sw >> 2) & 3;
  327. printf("Clock1 = %sMHz ", freq[clock]);
  328. clock = (sw >> 0) & 3;
  329. printf("Clock2 = %sMHz\n", freq[clock]);
  330. return 0;
  331. }
  332. #endif
  333. bool if_board_diff_clk(void)
  334. {
  335. #ifdef CONFIG_TARGET_LS1088AQDS
  336. u8 diff_conf = QIXIS_READ(brdcfg[11]);
  337. return diff_conf & 0x40;
  338. #else
  339. u8 diff_conf = QIXIS_READ(dutcfg[11]);
  340. return diff_conf & 0x80;
  341. #endif
  342. }
  343. unsigned long get_board_sys_clk(void)
  344. {
  345. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  346. switch (sysclk_conf & 0x0f) {
  347. case QIXIS_SYSCLK_83:
  348. return 83333333;
  349. case QIXIS_SYSCLK_100:
  350. return 100000000;
  351. case QIXIS_SYSCLK_125:
  352. return 125000000;
  353. case QIXIS_SYSCLK_133:
  354. return 133333333;
  355. case QIXIS_SYSCLK_150:
  356. return 150000000;
  357. case QIXIS_SYSCLK_160:
  358. return 160000000;
  359. case QIXIS_SYSCLK_166:
  360. return 166666666;
  361. }
  362. return 66666666;
  363. }
  364. unsigned long get_board_ddr_clk(void)
  365. {
  366. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  367. if (if_board_diff_clk())
  368. return get_board_sys_clk();
  369. switch ((ddrclk_conf & 0x30) >> 4) {
  370. case QIXIS_DDRCLK_100:
  371. return 100000000;
  372. case QIXIS_DDRCLK_125:
  373. return 125000000;
  374. case QIXIS_DDRCLK_133:
  375. return 133333333;
  376. }
  377. return 66666666;
  378. }
  379. #if !defined(CONFIG_SPL_BUILD)
  380. void board_retimer_init(void)
  381. {
  382. u8 reg;
  383. /* Retimer is connected to I2C1_CH5 */
  384. select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
  385. /* Access to Control/Shared register */
  386. reg = 0x0;
  387. #if !CONFIG_IS_ENABLED(DM_I2C)
  388. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  389. #else
  390. struct udevice *dev;
  391. i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
  392. dm_i2c_write(dev, 0xff, &reg, 1);
  393. #endif
  394. /* Read device revision and ID */
  395. #if !CONFIG_IS_ENABLED(DM_I2C)
  396. i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
  397. #else
  398. dm_i2c_read(dev, 1, &reg, 1);
  399. #endif
  400. debug("Retimer version id = 0x%x\n", reg);
  401. /* Enable Broadcast. All writes target all channel register sets */
  402. reg = 0x0c;
  403. #if !CONFIG_IS_ENABLED(DM_I2C)
  404. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  405. #else
  406. dm_i2c_write(dev, 0xff, &reg, 1);
  407. #endif
  408. /* Reset Channel Registers */
  409. #if !CONFIG_IS_ENABLED(DM_I2C)
  410. i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  411. #else
  412. dm_i2c_read(dev, 0, &reg, 1);
  413. #endif
  414. reg |= 0x4;
  415. #if !CONFIG_IS_ENABLED(DM_I2C)
  416. i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  417. #else
  418. dm_i2c_write(dev, 0, &reg, 1);
  419. #endif
  420. /* Set data rate as 10.3125 Gbps */
  421. reg = 0x90;
  422. #if !CONFIG_IS_ENABLED(DM_I2C)
  423. i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
  424. #else
  425. dm_i2c_write(dev, 0x60, &reg, 1);
  426. #endif
  427. reg = 0xb3;
  428. #if !CONFIG_IS_ENABLED(DM_I2C)
  429. i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
  430. #else
  431. dm_i2c_write(dev, 0x61, &reg, 1);
  432. #endif
  433. reg = 0x90;
  434. #if !CONFIG_IS_ENABLED(DM_I2C)
  435. i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
  436. #else
  437. dm_i2c_write(dev, 0x62, &reg, 1);
  438. #endif
  439. reg = 0xb3;
  440. #if !CONFIG_IS_ENABLED(DM_I2C)
  441. i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
  442. #else
  443. dm_i2c_write(dev, 0x63, &reg, 1);
  444. #endif
  445. reg = 0xcd;
  446. #if !CONFIG_IS_ENABLED(DM_I2C)
  447. i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
  448. #else
  449. dm_i2c_write(dev, 0x64, &reg, 1);
  450. #endif
  451. /* Select VCO Divider to full rate (000) */
  452. #if !CONFIG_IS_ENABLED(DM_I2C)
  453. i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
  454. #else
  455. dm_i2c_read(dev, 0x2F, &reg, 1);
  456. #endif
  457. reg &= 0x0f;
  458. reg |= 0x70;
  459. #if !CONFIG_IS_ENABLED(DM_I2C)
  460. i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
  461. #else
  462. dm_i2c_write(dev, 0x2F, &reg, 1);
  463. #endif
  464. #ifdef CONFIG_TARGET_LS1088AQDS
  465. /* Retimer is connected to I2C1_CH5 */
  466. select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
  467. /* Access to Control/Shared register */
  468. reg = 0x0;
  469. #if !CONFIG_IS_ENABLED(DM_I2C)
  470. i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
  471. #else
  472. i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
  473. dm_i2c_write(dev, 0xff, &reg, 1);
  474. #endif
  475. /* Read device revision and ID */
  476. #if !CONFIG_IS_ENABLED(DM_I2C)
  477. i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
  478. #else
  479. dm_i2c_read(dev, 1, &reg, 1);
  480. #endif
  481. debug("Retimer version id = 0x%x\n", reg);
  482. /* Enable Broadcast. All writes target all channel register sets */
  483. reg = 0x0c;
  484. #if !CONFIG_IS_ENABLED(DM_I2C)
  485. i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
  486. #else
  487. dm_i2c_write(dev, 0xff, &reg, 1);
  488. #endif
  489. /* Reset Channel Registers */
  490. #if !CONFIG_IS_ENABLED(DM_I2C)
  491. i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
  492. #else
  493. dm_i2c_read(dev, 0, &reg, 1);
  494. #endif
  495. reg |= 0x4;
  496. #if !CONFIG_IS_ENABLED(DM_I2C)
  497. i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
  498. #else
  499. dm_i2c_write(dev, 0, &reg, 1);
  500. #endif
  501. /* Set data rate as 10.3125 Gbps */
  502. reg = 0x90;
  503. #if !CONFIG_IS_ENABLED(DM_I2C)
  504. i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
  505. #else
  506. dm_i2c_write(dev, 0x60, &reg, 1);
  507. #endif
  508. reg = 0xb3;
  509. #if !CONFIG_IS_ENABLED(DM_I2C)
  510. i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
  511. #else
  512. dm_i2c_write(dev, 0x61, &reg, 1);
  513. #endif
  514. reg = 0x90;
  515. #if !CONFIG_IS_ENABLED(DM_I2C)
  516. i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
  517. #else
  518. dm_i2c_write(dev, 0x62, &reg, 1);
  519. #endif
  520. reg = 0xb3;
  521. #if !CONFIG_IS_ENABLED(DM_I2C)
  522. i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
  523. #else
  524. dm_i2c_write(dev, 0x63, &reg, 1);
  525. #endif
  526. reg = 0xcd;
  527. #if !CONFIG_IS_ENABLED(DM_I2C)
  528. i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
  529. #else
  530. dm_i2c_write(dev, 0x64, &reg, 1);
  531. #endif
  532. /* Select VCO Divider to full rate (000) */
  533. #if !CONFIG_IS_ENABLED(DM_I2C)
  534. i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
  535. #else
  536. dm_i2c_read(dev, 0x2F, &reg, 1);
  537. #endif
  538. reg &= 0x0f;
  539. reg |= 0x70;
  540. #if !CONFIG_IS_ENABLED(DM_I2C)
  541. i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
  542. #else
  543. dm_i2c_write(dev, 0x2F, &reg, 1);
  544. #endif
  545. #endif
  546. /*return the default channel*/
  547. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  548. }
  549. #ifdef CONFIG_MISC_INIT_R
  550. int misc_init_r(void)
  551. {
  552. #ifdef CONFIG_TARGET_LS1088ARDB
  553. u8 brdcfg5;
  554. if (hwconfig("esdhc-force-sd")) {
  555. brdcfg5 = QIXIS_READ(brdcfg[5]);
  556. brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
  557. brdcfg5 |= BRDCFG5_FORCE_SD;
  558. QIXIS_WRITE(brdcfg[5], brdcfg5);
  559. }
  560. #endif
  561. #ifdef CONFIG_TARGET_LS1088AQDS
  562. u8 brdcfg4, brdcfg5;
  563. if (hwconfig("dspi-on-board")) {
  564. brdcfg4 = QIXIS_READ(brdcfg[4]);
  565. brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
  566. brdcfg4 |= BRDCFG4_SPI;
  567. QIXIS_WRITE(brdcfg[4], brdcfg4);
  568. brdcfg5 = QIXIS_READ(brdcfg[5]);
  569. brdcfg5 &= ~BRDCFG5_SPR_MASK;
  570. brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
  571. QIXIS_WRITE(brdcfg[5], brdcfg5);
  572. } else if (hwconfig("dspi-off-board")) {
  573. brdcfg4 = QIXIS_READ(brdcfg[4]);
  574. brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
  575. brdcfg4 |= BRDCFG4_SPI;
  576. QIXIS_WRITE(brdcfg[4], brdcfg4);
  577. brdcfg5 = QIXIS_READ(brdcfg[5]);
  578. brdcfg5 &= ~BRDCFG5_SPR_MASK;
  579. brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
  580. QIXIS_WRITE(brdcfg[5], brdcfg5);
  581. }
  582. #endif
  583. return 0;
  584. }
  585. #endif
  586. #endif
  587. int i2c_multiplexer_select_vid_channel(u8 channel)
  588. {
  589. return select_i2c_ch_pca9547(channel, 0);
  590. }
  591. #ifdef CONFIG_TARGET_LS1088AQDS
  592. /* read the current value(SVDD) of the LTM Regulator Voltage */
  593. int get_serdes_volt(void)
  594. {
  595. int ret, vcode = 0;
  596. u8 chan = PWM_CHANNEL0;
  597. /* Select the PAGE 0 using PMBus commands PAGE for VDD */
  598. #if !CONFIG_IS_ENABLED(DM_I2C)
  599. ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
  600. PMBUS_CMD_PAGE, 1, &chan, 1);
  601. #else
  602. struct udevice *dev;
  603. ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
  604. if (!ret)
  605. ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
  606. &chan, 1);
  607. #endif
  608. if (ret) {
  609. printf("VID: failed to select VDD Page 0\n");
  610. return ret;
  611. }
  612. /* Read the output voltage using PMBus command READ_VOUT */
  613. #if !CONFIG_IS_ENABLED(DM_I2C)
  614. ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
  615. PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
  616. #else
  617. dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
  618. #endif
  619. if (ret) {
  620. printf("VID: failed to read the volatge\n");
  621. return ret;
  622. }
  623. return vcode;
  624. }
  625. int set_serdes_volt(int svdd)
  626. {
  627. int ret, vdd_last;
  628. u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
  629. svdd & 0xFF, (svdd & 0xFF00) >> 8};
  630. /* Write the desired voltage code to the SVDD regulator */
  631. #if !CONFIG_IS_ENABLED(DM_I2C)
  632. ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
  633. PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
  634. #else
  635. struct udevice *dev;
  636. ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
  637. if (!ret)
  638. ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
  639. (void *)&buff, 5);
  640. #endif
  641. if (ret) {
  642. printf("VID: I2C failed to write to the volatge regulator\n");
  643. return -1;
  644. }
  645. /* Wait for the volatge to get to the desired value */
  646. do {
  647. vdd_last = get_serdes_volt();
  648. if (vdd_last < 0) {
  649. printf("VID: Couldn't read sensor abort VID adjust\n");
  650. return -1;
  651. }
  652. } while (vdd_last != svdd);
  653. return 1;
  654. }
  655. #else
  656. int get_serdes_volt(void)
  657. {
  658. return 0;
  659. }
  660. int set_serdes_volt(int svdd)
  661. {
  662. int ret;
  663. u8 brdcfg4;
  664. printf("SVDD changing of RDB\n");
  665. /* Read the BRDCFG54 via CLPD */
  666. #if !CONFIG_IS_ENABLED(DM_I2C)
  667. ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
  668. QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
  669. #else
  670. struct udevice *dev;
  671. ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
  672. if (!ret)
  673. ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
  674. (void *)&brdcfg4, 1);
  675. #endif
  676. if (ret) {
  677. printf("VID: I2C failed to read the CPLD BRDCFG4\n");
  678. return -1;
  679. }
  680. brdcfg4 = brdcfg4 | 0x08;
  681. /* Write to the BRDCFG4 */
  682. #if !CONFIG_IS_ENABLED(DM_I2C)
  683. ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
  684. QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
  685. #else
  686. ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
  687. (void *)&brdcfg4, 1);
  688. #endif
  689. if (ret) {
  690. debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
  691. return -1;
  692. }
  693. /* Wait for the volatge to get to the desired value */
  694. udelay(10000);
  695. return 1;
  696. }
  697. #endif
  698. /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
  699. int board_adjust_vdd(int vdd)
  700. {
  701. int ret = 0;
  702. debug("%s: vdd = %d\n", __func__, vdd);
  703. /* Special settings to be performed when voltage is 900mV */
  704. if (vdd == 900) {
  705. ret = setup_serdes_volt(vdd);
  706. if (ret < 0) {
  707. ret = -1;
  708. goto exit;
  709. }
  710. }
  711. exit:
  712. return ret;
  713. }
  714. #if !defined(CONFIG_SPL_BUILD)
  715. int board_init(void)
  716. {
  717. init_final_memctl_regs();
  718. #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
  719. u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  720. #endif
  721. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  722. board_retimer_init();
  723. #ifdef CONFIG_ENV_IS_NOWHERE
  724. gd->env_addr = (ulong)&default_environment[0];
  725. #endif
  726. #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
  727. /* invert AQR105 IRQ pins polarity */
  728. out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
  729. #endif
  730. #ifdef CONFIG_FSL_CAAM
  731. sec_init();
  732. #endif
  733. #ifdef CONFIG_FSL_LS_PPA
  734. ppa_init();
  735. #endif
  736. #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
  737. pci_init();
  738. #endif
  739. return 0;
  740. }
  741. void detail_board_ddr_info(void)
  742. {
  743. puts("\nDDR ");
  744. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  745. print_ddr_info(0);
  746. }
  747. #ifdef CONFIG_FSL_MC_ENET
  748. void board_quiesce_devices(void)
  749. {
  750. fsl_mc_ldpaa_exit(gd->bd);
  751. }
  752. void fdt_fixup_board_enet(void *fdt)
  753. {
  754. int offset;
  755. offset = fdt_path_offset(fdt, "/fsl-mc");
  756. if (offset < 0)
  757. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  758. if (offset < 0) {
  759. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  760. __func__, offset);
  761. return;
  762. }
  763. if (get_mc_boot_status() == 0 &&
  764. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
  765. fdt_status_okay(fdt, offset);
  766. else
  767. fdt_status_fail(fdt, offset);
  768. }
  769. #endif
  770. #ifdef CONFIG_OF_BOARD_SETUP
  771. void fsl_fdt_fixup_flash(void *fdt)
  772. {
  773. int offset;
  774. #ifdef CONFIG_TFABOOT
  775. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  776. u32 val;
  777. #endif
  778. /*
  779. * IFC-NOR and QSPI are muxed on SoC.
  780. * So disable IFC node in dts if QSPI is enabled or
  781. * disable QSPI node in dts in case QSPI is not enabled.
  782. */
  783. #ifdef CONFIG_TFABOOT
  784. enum boot_src src = get_boot_src();
  785. bool disable_ifc = false;
  786. switch (src) {
  787. case BOOT_SOURCE_IFC_NOR:
  788. disable_ifc = false;
  789. break;
  790. case BOOT_SOURCE_QSPI_NOR:
  791. disable_ifc = true;
  792. break;
  793. default:
  794. val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  795. if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  796. disable_ifc = true;
  797. break;
  798. }
  799. if (disable_ifc) {
  800. offset = fdt_path_offset(fdt, "/soc/ifc/nor");
  801. if (offset < 0)
  802. offset = fdt_path_offset(fdt, "/ifc/nor");
  803. } else {
  804. offset = fdt_path_offset(fdt, "/soc/quadspi");
  805. if (offset < 0)
  806. offset = fdt_path_offset(fdt, "/quadspi");
  807. }
  808. #else
  809. #ifdef CONFIG_FSL_QSPI
  810. offset = fdt_path_offset(fdt, "/soc/ifc/nor");
  811. if (offset < 0)
  812. offset = fdt_path_offset(fdt, "/ifc/nor");
  813. #else
  814. offset = fdt_path_offset(fdt, "/soc/quadspi");
  815. if (offset < 0)
  816. offset = fdt_path_offset(fdt, "/quadspi");
  817. #endif
  818. #endif
  819. if (offset < 0)
  820. return;
  821. fdt_status_disabled(fdt, offset);
  822. }
  823. int ft_board_setup(void *blob, struct bd_info *bd)
  824. {
  825. int i;
  826. u16 mc_memory_bank = 0;
  827. u64 *base;
  828. u64 *size;
  829. u64 mc_memory_base = 0;
  830. u64 mc_memory_size = 0;
  831. u16 total_memory_banks;
  832. ft_cpu_setup(blob, bd);
  833. fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
  834. if (mc_memory_base != 0)
  835. mc_memory_bank++;
  836. total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
  837. base = calloc(total_memory_banks, sizeof(u64));
  838. size = calloc(total_memory_banks, sizeof(u64));
  839. /* fixup DT for the two GPP DDR banks */
  840. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  841. base[i] = gd->bd->bi_dram[i].start;
  842. size[i] = gd->bd->bi_dram[i].size;
  843. }
  844. #ifdef CONFIG_RESV_RAM
  845. /* reduce size if reserved memory is within this bank */
  846. if (gd->arch.resv_ram >= base[0] &&
  847. gd->arch.resv_ram < base[0] + size[0])
  848. size[0] = gd->arch.resv_ram - base[0];
  849. else if (gd->arch.resv_ram >= base[1] &&
  850. gd->arch.resv_ram < base[1] + size[1])
  851. size[1] = gd->arch.resv_ram - base[1];
  852. #endif
  853. if (mc_memory_base != 0) {
  854. for (i = 0; i <= total_memory_banks; i++) {
  855. if (base[i] == 0 && size[i] == 0) {
  856. base[i] = mc_memory_base;
  857. size[i] = mc_memory_size;
  858. break;
  859. }
  860. }
  861. }
  862. fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
  863. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  864. fsl_fdt_fixup_flash(blob);
  865. #ifdef CONFIG_FSL_MC_ENET
  866. fdt_fixup_board_enet(blob);
  867. #endif
  868. fdt_fixup_icid(blob);
  869. if (is_pb_board())
  870. fixup_ls1088ardb_pb_banner(blob);
  871. return 0;
  872. }
  873. #endif
  874. #endif /* defined(CONFIG_SPL_BUILD) */
  875. #ifdef CONFIG_TFABOOT
  876. #ifdef CONFIG_MTD_NOR_FLASH
  877. int is_flash_available(void)
  878. {
  879. char *env_hwconfig = env_get("hwconfig");
  880. enum boot_src src = get_boot_src();
  881. int is_nor_flash_available = 1;
  882. switch (src) {
  883. case BOOT_SOURCE_IFC_NOR:
  884. is_nor_flash_available = 1;
  885. break;
  886. case BOOT_SOURCE_QSPI_NOR:
  887. is_nor_flash_available = 0;
  888. break;
  889. /*
  890. * In Case of SD boot,if qspi is defined in env_hwconfig
  891. * disable nor flash probe.
  892. */
  893. default:
  894. if (hwconfig_f("qspi", env_hwconfig))
  895. is_nor_flash_available = 0;
  896. break;
  897. }
  898. return is_nor_flash_available;
  899. }
  900. #endif
  901. #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  902. void *env_sf_get_env_addr(void)
  903. {
  904. return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
  905. }
  906. #endif
  907. #endif