eth_ls1088ardb.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <net.h>
  8. #include <netdev.h>
  9. #include <malloc.h>
  10. #include <fsl_mdio.h>
  11. #include <miiphy.h>
  12. #include <phy.h>
  13. #include <fm_eth.h>
  14. #include <asm/io.h>
  15. #include <exports.h>
  16. #include <asm/arch/fsl_serdes.h>
  17. #include <fsl-mc/fsl_mc.h>
  18. #include <fsl-mc/ldpaa_wriop.h>
  19. #ifndef CONFIG_DM_ETH
  20. int board_eth_init(struct bd_info *bis)
  21. {
  22. #if defined(CONFIG_FSL_MC_ENET)
  23. int i, interface;
  24. struct memac_mdio_info mdio_info;
  25. struct mii_dev *dev;
  26. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  27. struct memac_mdio_controller *reg;
  28. u32 srds_s1, cfg;
  29. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  30. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  31. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  32. srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
  33. reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  34. mdio_info.regs = reg;
  35. mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  36. /* Register the EMI 1 */
  37. fm_memac_mdio_init(bis, &mdio_info);
  38. reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  39. mdio_info.regs = reg;
  40. mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  41. /* Register the EMI 2 */
  42. fm_memac_mdio_init(bis, &mdio_info);
  43. switch (srds_s1) {
  44. case 0x1D:
  45. /*
  46. * XFI does not need a PHY to work, but to avoid U-boot use
  47. * default PHY address which is zero to a MAC when it found
  48. * a MAC has no PHY address, we give a PHY address to XFI
  49. * MAC error.
  50. */
  51. wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a);
  52. wriop_set_phy_address(WRIOP1_DPMAC2, 0, AQ_PHY_ADDR1);
  53. wriop_set_phy_address(WRIOP1_DPMAC3, 0, QSGMII1_PORT1_PHY_ADDR);
  54. wriop_set_phy_address(WRIOP1_DPMAC4, 0, QSGMII1_PORT2_PHY_ADDR);
  55. wriop_set_phy_address(WRIOP1_DPMAC5, 0, QSGMII1_PORT3_PHY_ADDR);
  56. wriop_set_phy_address(WRIOP1_DPMAC6, 0, QSGMII1_PORT4_PHY_ADDR);
  57. wriop_set_phy_address(WRIOP1_DPMAC7, 0, QSGMII2_PORT1_PHY_ADDR);
  58. wriop_set_phy_address(WRIOP1_DPMAC8, 0, QSGMII2_PORT2_PHY_ADDR);
  59. wriop_set_phy_address(WRIOP1_DPMAC9, 0, QSGMII2_PORT3_PHY_ADDR);
  60. wriop_set_phy_address(WRIOP1_DPMAC10, 0,
  61. QSGMII2_PORT4_PHY_ADDR);
  62. break;
  63. default:
  64. printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n",
  65. srds_s1);
  66. break;
  67. }
  68. for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) {
  69. interface = wriop_get_enet_if(i);
  70. switch (interface) {
  71. case PHY_INTERFACE_MODE_QSGMII:
  72. dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
  73. wriop_set_mdio(i, dev);
  74. break;
  75. default:
  76. break;
  77. }
  78. }
  79. dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  80. wriop_set_mdio(WRIOP1_DPMAC2, dev);
  81. cpu_eth_init(bis);
  82. #endif /* CONFIG_FMAN_ENET */
  83. return pci_eth_init(bis);
  84. }
  85. #endif
  86. #if defined(CONFIG_RESET_PHY_R)
  87. void reset_phy(void)
  88. {
  89. mc_env_boot();
  90. }
  91. #endif /* CONFIG_RESET_PHY_R */