ddr.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. #include <log.h>
  9. #include <asm/arch/soc.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/global_data.h>
  12. #include "ddr.h"
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  15. static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts)
  16. {
  17. int vdd;
  18. vdd = get_core_volt_from_fuse();
  19. /* Nothing to do for silicons doesn't support VID */
  20. if (vdd < 0)
  21. return;
  22. if (vdd == 900) {
  23. popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN;
  24. debug("VID: configure DDR to support 900 mV\n");
  25. }
  26. }
  27. #endif
  28. void fsl_ddr_board_options(memctl_options_t *popts,
  29. dimm_params_t *pdimm,
  30. unsigned int ctrl_num)
  31. {
  32. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  33. ulong ddr_freq;
  34. if (ctrl_num > 1) {
  35. printf("Not supported controller number %d\n", ctrl_num);
  36. return;
  37. }
  38. if (!pdimm->n_ranks)
  39. return;
  40. /*
  41. * we use identical timing for all slots. If needed, change the code
  42. * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  43. */
  44. pbsp = udimms[0];
  45. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  46. * freqency and n_banks specified in board_specific_parameters table.
  47. */
  48. ddr_freq = get_ddr_freq(0) / 1000000;
  49. while (pbsp->datarate_mhz_high) {
  50. if (pbsp->n_ranks == pdimm->n_ranks) {
  51. if (ddr_freq <= pbsp->datarate_mhz_high) {
  52. popts->clk_adjust = pbsp->clk_adjust;
  53. popts->wrlvl_start = pbsp->wrlvl_start;
  54. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  55. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  56. goto found;
  57. }
  58. pbsp_highest = pbsp;
  59. }
  60. pbsp++;
  61. }
  62. if (pbsp_highest) {
  63. printf("Error: board specific timing not found for %lu MT/s\n",
  64. ddr_freq);
  65. printf("Trying to use the highest speed (%u) parameters\n",
  66. pbsp_highest->datarate_mhz_high);
  67. popts->clk_adjust = pbsp_highest->clk_adjust;
  68. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  69. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  70. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  71. } else {
  72. panic("DIMM is not supported by this board");
  73. }
  74. found:
  75. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  76. "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  77. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  78. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  79. pbsp->wrlvl_ctl_3);
  80. popts->half_strength_driver_enable = 0;
  81. /*
  82. * Write leveling override
  83. */
  84. popts->wrlvl_override = 1;
  85. popts->wrlvl_sample = 0xf;
  86. /* Enable ZQ calibration */
  87. popts->zq_en = 1;
  88. /* Enable DDR hashing */
  89. popts->addr_hash = 1;
  90. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
  91. #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  92. fsl_ddr_setup_0v9_volt(popts);
  93. #endif
  94. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
  95. DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
  96. }
  97. #ifdef CONFIG_TFABOOT
  98. int fsl_initdram(void)
  99. {
  100. gd->ram_size = tfa_get_dram_size();
  101. if (!gd->ram_size)
  102. gd->ram_size = fsl_ddr_sdram_size();
  103. return 0;
  104. }
  105. #else
  106. int fsl_initdram(void)
  107. {
  108. puts("Initializing DDR....using SPD\n");
  109. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  110. gd->ram_size = fsl_ddr_sdram_size();
  111. #else
  112. gd->ram_size = fsl_ddr_sdram();
  113. #endif
  114. return 0;
  115. }
  116. #endif /* CONFIG_TFABOOT */