ls1046ardb.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <fdt_support.h>
  8. #include <init.h>
  9. #include <asm/global_data.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/fsl_serdes.h>
  13. #include <asm/arch/ppa.h>
  14. #include <asm/arch/soc.h>
  15. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  16. #include <hwconfig.h>
  17. #include <ahci.h>
  18. #include <mmc.h>
  19. #include <scsi.h>
  20. #include <fm_eth.h>
  21. #include <fsl_csu.h>
  22. #include <fsl_esdhc.h>
  23. #include <power/mc34vr500_pmic.h>
  24. #include "cpld.h"
  25. #include <fsl_sec.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. int board_early_init_f(void)
  28. {
  29. fsl_lsch2_early_init_f();
  30. return 0;
  31. }
  32. #ifndef CONFIG_SPL_BUILD
  33. int checkboard(void)
  34. {
  35. static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
  36. u8 cfg_rcw_src1, cfg_rcw_src2;
  37. u16 cfg_rcw_src;
  38. u8 sd1refclk_sel;
  39. puts("Board: LS1046ARDB, boot from ");
  40. cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
  41. cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
  42. cpld_rev_bit(&cfg_rcw_src1);
  43. cfg_rcw_src = cfg_rcw_src1;
  44. cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
  45. if (cfg_rcw_src == 0x44)
  46. printf("QSPI vBank %d\n", CPLD_READ(vbank));
  47. else if (cfg_rcw_src == 0x40)
  48. puts("SD\n");
  49. else
  50. puts("Invalid setting of SW5\n");
  51. printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
  52. CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
  53. puts("SERDES Reference Clocks:\n");
  54. sd1refclk_sel = CPLD_READ(sd1refclk_sel);
  55. printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
  56. return 0;
  57. }
  58. int board_init(void)
  59. {
  60. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  61. #ifdef CONFIG_NXP_ESBC
  62. /*
  63. * In case of Secure Boot, the IBR configures the SMMU
  64. * to allow only Secure transactions.
  65. * SMMU must be reset in bypass mode.
  66. * Set the ClientPD bit and Clear the USFCFG Bit
  67. */
  68. u32 val;
  69. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  70. out_le32(SMMU_SCR0, val);
  71. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  72. out_le32(SMMU_NSCR0, val);
  73. #endif
  74. #ifdef CONFIG_FSL_CAAM
  75. sec_init();
  76. #endif
  77. #ifdef CONFIG_FSL_LS_PPA
  78. ppa_init();
  79. #endif
  80. /* invert AQR105 IRQ pins polarity */
  81. out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
  82. return 0;
  83. }
  84. int board_setup_core_volt(u32 vdd)
  85. {
  86. bool en_0v9;
  87. en_0v9 = (vdd == 900) ? true : false;
  88. cpld_select_core_volt(en_0v9);
  89. return 0;
  90. }
  91. int get_serdes_volt(void)
  92. {
  93. return mc34vr500_get_sw_volt(SW4);
  94. }
  95. int set_serdes_volt(int svdd)
  96. {
  97. return mc34vr500_set_sw_volt(SW4, svdd);
  98. }
  99. int power_init_board(void)
  100. {
  101. int ret;
  102. ret = power_mc34vr500_init(0);
  103. if (ret)
  104. return ret;
  105. setup_chip_volt();
  106. return 0;
  107. }
  108. void config_board_mux(void)
  109. {
  110. #ifdef CONFIG_HAS_FSL_XHCI_USB
  111. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  112. u32 usb_pwrfault;
  113. /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
  114. out_be32(&scfg->rcwpmuxcr0, 0x3300);
  115. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  116. usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
  117. SCFG_USBPWRFAULT_USB3_SHIFT) |
  118. (SCFG_USBPWRFAULT_DEDICATED <<
  119. SCFG_USBPWRFAULT_USB2_SHIFT) |
  120. (SCFG_USBPWRFAULT_SHARED <<
  121. SCFG_USBPWRFAULT_USB1_SHIFT);
  122. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  123. #endif
  124. }
  125. #ifdef CONFIG_MISC_INIT_R
  126. int misc_init_r(void)
  127. {
  128. config_board_mux();
  129. return 0;
  130. }
  131. #endif
  132. int ft_board_setup(void *blob, struct bd_info *bd)
  133. {
  134. u64 base[CONFIG_NR_DRAM_BANKS];
  135. u64 size[CONFIG_NR_DRAM_BANKS];
  136. /* fixup DT for the two DDR banks */
  137. base[0] = gd->bd->bi_dram[0].start;
  138. size[0] = gd->bd->bi_dram[0].size;
  139. base[1] = gd->bd->bi_dram[1].start;
  140. size[1] = gd->bd->bi_dram[1].size;
  141. fdt_fixup_memory_banks(blob, base, size, 2);
  142. ft_cpu_setup(blob, bd);
  143. #ifdef CONFIG_SYS_DPAA_FMAN
  144. #ifndef CONFIG_DM_ETH
  145. fdt_fixup_fman_ethernet(blob);
  146. #endif
  147. #endif
  148. fdt_fixup_icid(blob);
  149. return 0;
  150. }
  151. #endif