ddr.h 1.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __DDR_H__
  6. #define __DDR_H__
  7. void erratum_a008850_post(void);
  8. struct board_specific_parameters {
  9. u32 n_ranks;
  10. u32 datarate_mhz_high;
  11. u32 rank_gb;
  12. u32 clk_adjust;
  13. u32 wrlvl_start;
  14. u32 wrlvl_ctl_2;
  15. u32 wrlvl_ctl_3;
  16. };
  17. /*
  18. * These tables contain all valid speeds we want to override with board
  19. * specific parameters. datarate_mhz_high values need to be in ascending order
  20. * for each n_ranks group.
  21. */
  22. static const struct board_specific_parameters udimm0[] = {
  23. /*
  24. * memory controller 0
  25. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  26. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  27. */
  28. {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
  29. {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
  30. {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
  31. {2, 2300, 0, 8, 7, 0x08090A0E, 0x1011120C,},
  32. {}
  33. };
  34. static const struct board_specific_parameters *udimms[] = {
  35. udimm0,
  36. };
  37. static const struct board_specific_parameters rdimm0[] = {
  38. /*
  39. * memory controller 0
  40. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  41. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  42. */
  43. {2, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,},
  44. {2, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,},
  45. {2, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,},
  46. {1, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,},
  47. {1, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,},
  48. {1, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,},
  49. {}
  50. };
  51. static const struct board_specific_parameters *rdimms[] = {
  52. rdimm0,
  53. };
  54. #endif