ddr.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. #include <asm/global_data.h>
  9. #include "ddr.h"
  10. #ifdef CONFIG_FSL_DEEP_SLEEP
  11. #include <fsl_sleep.h>
  12. #endif
  13. #include <log.h>
  14. #include <asm/arch/clock.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. void fsl_ddr_board_options(memctl_options_t *popts,
  17. dimm_params_t *pdimm,
  18. unsigned int ctrl_num)
  19. {
  20. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  21. ulong ddr_freq;
  22. if (ctrl_num > 1) {
  23. printf("Not supported controller number %d\n", ctrl_num);
  24. return;
  25. }
  26. if (!pdimm->n_ranks)
  27. return;
  28. if (popts->registered_dimm_en)
  29. pbsp = rdimms[0];
  30. else
  31. pbsp = udimms[0];
  32. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  33. * freqency and n_banks specified in board_specific_parameters table.
  34. */
  35. ddr_freq = get_ddr_freq(0) / 1000000;
  36. while (pbsp->datarate_mhz_high) {
  37. if (pbsp->n_ranks == pdimm->n_ranks) {
  38. if (ddr_freq <= pbsp->datarate_mhz_high) {
  39. popts->clk_adjust = pbsp->clk_adjust;
  40. popts->wrlvl_start = pbsp->wrlvl_start;
  41. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  42. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  43. goto found;
  44. }
  45. pbsp_highest = pbsp;
  46. }
  47. pbsp++;
  48. }
  49. if (pbsp_highest) {
  50. printf("Error: board specific timing not found for %lu MT/s\n",
  51. ddr_freq);
  52. printf("Trying to use the highest speed (%u) parameters\n",
  53. pbsp_highest->datarate_mhz_high);
  54. popts->clk_adjust = pbsp_highest->clk_adjust;
  55. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  56. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  57. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  58. } else {
  59. panic("DIMM is not supported by this board");
  60. }
  61. found:
  62. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  63. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  64. popts->data_bus_width = 0; /* 64-bit data bus */
  65. popts->bstopre = 0; /* enable auto precharge */
  66. /*
  67. * Factors to consider for half-strength driver enable:
  68. * - number of DIMMs installed
  69. */
  70. popts->half_strength_driver_enable = 0;
  71. /*
  72. * Write leveling override
  73. */
  74. popts->wrlvl_override = 1;
  75. popts->wrlvl_sample = 0xf;
  76. /*
  77. * Rtt and Rtt_WR override
  78. */
  79. popts->rtt_override = 0;
  80. /* Enable ZQ calibration */
  81. popts->zq_en = 1;
  82. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  83. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  84. DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
  85. /* optimize cpo for erratum A-009942 */
  86. popts->cpo_sample = 0x61;
  87. }
  88. #ifdef CONFIG_TFABOOT
  89. int fsl_initdram(void)
  90. {
  91. gd->ram_size = tfa_get_dram_size();
  92. if (!gd->ram_size)
  93. gd->ram_size = fsl_ddr_sdram_size();
  94. return 0;
  95. }
  96. #else
  97. int fsl_initdram(void)
  98. {
  99. phys_size_t dram_size;
  100. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  101. gd->ram_size = fsl_ddr_sdram_size();
  102. return 0;
  103. #else
  104. puts("Initializing DDR....using SPD\n");
  105. dram_size = fsl_ddr_sdram();
  106. #endif
  107. erratum_a008850_post();
  108. gd->ram_size = dram_size;
  109. return 0;
  110. }
  111. #endif