ls1021atsn.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright 2016-2019 NXP Semiconductors
  3. */
  4. #include <common.h>
  5. #include <clock_legacy.h>
  6. #include <fdt_support.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch-ls102xa/ls102xa_soc.h>
  10. #include <asm/arch/ls102xa_devdis.h>
  11. #include <asm/arch/immap_ls102xa.h>
  12. #include <asm/arch/ls102xa_soc.h>
  13. #include <asm/arch/fsl_serdes.h>
  14. #include <asm/global_data.h>
  15. #include <linux/delay.h>
  16. #include "../common/sleep.h"
  17. #include <fsl_validate.h>
  18. #include <fsl_immap.h>
  19. #include <fsl_csu.h>
  20. #include <netdev.h>
  21. #include <spl.h>
  22. #ifdef CONFIG_U_QE
  23. #include <fsl_qe.h>
  24. #endif
  25. DECLARE_GLOBAL_DATA_PTR;
  26. static void ddrmc_init(void)
  27. {
  28. #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  29. struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  30. u32 temp_sdram_cfg, tmp;
  31. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  32. out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  33. out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  34. out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  35. out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  36. out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  37. out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  38. out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  39. out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  40. #ifdef CONFIG_DEEP_SLEEP
  41. if (is_warm_boot()) {
  42. out_be32(&ddr->sdram_cfg_2,
  43. DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  44. out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  45. out_be32(&ddr->init_ext_addr, (1 << 31));
  46. /* DRAM VRef will not be trained */
  47. out_be32(&ddr->ddr_cdr2,
  48. DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  49. } else
  50. #endif
  51. {
  52. out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  53. out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  54. }
  55. out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  56. out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  57. out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  58. out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  59. out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  60. out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  61. out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  62. out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  63. out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  64. out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  65. /* DDR erratum A-009942 */
  66. tmp = in_be32(&ddr->debug[28]);
  67. out_be32(&ddr->debug[28], tmp | 0x0070006f);
  68. udelay(1);
  69. #ifdef CONFIG_DEEP_SLEEP
  70. if (is_warm_boot()) {
  71. /* enter self-refresh */
  72. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  73. temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  74. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  75. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  76. } else
  77. #endif
  78. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  79. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  80. #ifdef CONFIG_DEEP_SLEEP
  81. if (is_warm_boot()) {
  82. /* exit self-refresh */
  83. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  84. temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
  85. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  86. }
  87. #endif
  88. #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
  89. }
  90. int dram_init(void)
  91. {
  92. ddrmc_init();
  93. erratum_a008850_post();
  94. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  95. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  96. fsl_dp_resume();
  97. #endif
  98. return 0;
  99. }
  100. int board_eth_init(struct bd_info *bis)
  101. {
  102. return pci_eth_init(bis);
  103. }
  104. int board_early_init_f(void)
  105. {
  106. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  107. #ifdef CONFIG_TSEC_ENET
  108. /*
  109. * Clear BD & FR bits for big endian BD's and frame data (aka set
  110. * correct eTSEC endianness). This is crucial in ensuring that it does
  111. * not report Data Parity Errors in its RX/TX FIFOs when attempting to
  112. * send traffic.
  113. */
  114. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  115. /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
  116. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  117. #endif
  118. arch_soc_init();
  119. #if defined(CONFIG_DEEP_SLEEP)
  120. if (is_warm_boot()) {
  121. timer_init();
  122. dram_init();
  123. }
  124. #endif
  125. return 0;
  126. }
  127. #ifdef CONFIG_SPL_BUILD
  128. void board_init_f(ulong dummy)
  129. {
  130. void (*second_uboot)(void);
  131. /* Clear the BSS */
  132. memset(__bss_start, 0, __bss_end - __bss_start);
  133. get_clocks();
  134. #if defined(CONFIG_DEEP_SLEEP)
  135. if (is_warm_boot())
  136. fsl_dp_disable_console();
  137. #endif
  138. preloader_console_init();
  139. dram_init();
  140. /* Allow OCRAM access permission as R/W */
  141. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  142. enable_layerscape_ns_access();
  143. enable_layerscape_ns_access();
  144. #endif
  145. /*
  146. * if it is woken up from deep sleep, then jump to second
  147. * stage U-Boot and continue executing without recopying
  148. * it from SD since it has already been reserved in memory
  149. * in last boot.
  150. */
  151. if (is_warm_boot()) {
  152. second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
  153. second_uboot();
  154. }
  155. board_init_r(NULL, 0);
  156. }
  157. #endif
  158. int board_init(void)
  159. {
  160. #ifndef CONFIG_SYS_FSL_NO_SERDES
  161. fsl_serdes_init();
  162. #endif
  163. ls102xa_smmu_stream_id_init();
  164. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  165. enable_layerscape_ns_access();
  166. #endif
  167. #ifdef CONFIG_U_QE
  168. u_qe_init();
  169. #endif
  170. return 0;
  171. }
  172. #if defined(CONFIG_SPL_BUILD)
  173. void spl_board_init(void)
  174. {
  175. ls102xa_smmu_stream_id_init();
  176. }
  177. #endif
  178. #ifdef CONFIG_BOARD_LATE_INIT
  179. int board_late_init(void)
  180. {
  181. #ifdef CONFIG_CHAIN_OF_TRUST
  182. fsl_setenv_chain_of_trust();
  183. #endif
  184. return 0;
  185. }
  186. #endif
  187. #if defined(CONFIG_MISC_INIT_R)
  188. int misc_init_r(void)
  189. {
  190. #ifdef CONFIG_FSL_DEVICE_DISABLE
  191. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  192. #endif
  193. #ifdef CONFIG_FSL_CAAM
  194. return sec_init();
  195. #endif
  196. }
  197. #endif
  198. #if defined(CONFIG_DEEP_SLEEP)
  199. void board_sleep_prepare(void)
  200. {
  201. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  202. enable_layerscape_ns_access();
  203. #endif
  204. }
  205. #endif
  206. int ft_board_setup(void *blob, struct bd_info *bd)
  207. {
  208. ft_cpu_setup(blob, bd);
  209. #ifdef CONFIG_PCI
  210. ft_pci_setup(blob, bd);
  211. #endif
  212. return 0;
  213. }