ls1012ardb.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <fdt_support.h>
  8. #include <hang.h>
  9. #include <i2c.h>
  10. #include <asm/cache.h>
  11. #include <init.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/fsl_serdes.h>
  16. #ifdef CONFIG_FSL_LS_PPA
  17. #include <asm/arch/ppa.h>
  18. #endif
  19. #include <asm/arch/mmu.h>
  20. #include <asm/arch/soc.h>
  21. #include <hwconfig.h>
  22. #include <ahci.h>
  23. #include <mmc.h>
  24. #include <scsi.h>
  25. #include <fsl_esdhc.h>
  26. #include <env_internal.h>
  27. #include <fsl_mmdc.h>
  28. #include <netdev.h>
  29. #include <fsl_sec.h>
  30. #include <net/pfe_eth/pfe/pfe_hw.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #define BOOT_FROM_UPPER_BANK 0x2
  33. #define BOOT_FROM_LOWER_BANK 0x1
  34. int checkboard(void)
  35. {
  36. #ifdef CONFIG_TARGET_LS1012ARDB
  37. u8 in1;
  38. int ret, bus_num = 0;
  39. puts("Board: LS1012ARDB ");
  40. /* Initialize i2c early for Serial flash bank information */
  41. #if CONFIG_IS_ENABLED(DM_I2C)
  42. struct udevice *dev;
  43. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
  44. 1, &dev);
  45. if (ret) {
  46. printf("%s: Cannot find udev for a bus %d\n", __func__,
  47. bus_num);
  48. return -ENXIO;
  49. }
  50. ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
  51. #else /* Non DM I2C support - will be removed */
  52. i2c_set_bus_num(bus_num);
  53. ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
  54. #endif
  55. if (ret < 0) {
  56. printf("Error reading i2c boot information!\n");
  57. return 0; /* Don't want to hang() on this error */
  58. }
  59. puts("Version");
  60. switch (in1 & SW_REV_MASK) {
  61. case SW_REV_A:
  62. puts(": RevA");
  63. break;
  64. case SW_REV_B:
  65. puts(": RevB");
  66. break;
  67. case SW_REV_C:
  68. puts(": RevC");
  69. break;
  70. case SW_REV_C1:
  71. puts(": RevC1");
  72. break;
  73. case SW_REV_C2:
  74. puts(": RevC2");
  75. break;
  76. case SW_REV_D:
  77. puts(": RevD");
  78. break;
  79. case SW_REV_E:
  80. puts(": RevE");
  81. break;
  82. default:
  83. puts(": unknown");
  84. break;
  85. }
  86. printf(", boot from QSPI");
  87. if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
  88. puts(": emu\n");
  89. else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
  90. puts(": bank1\n");
  91. else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
  92. puts(": bank2\n");
  93. else
  94. puts("unknown\n");
  95. #else
  96. puts("Board: LS1012A2G5RDB ");
  97. #endif
  98. return 0;
  99. }
  100. #ifdef CONFIG_TFABOOT
  101. int dram_init(void)
  102. {
  103. gd->ram_size = tfa_get_dram_size();
  104. if (!gd->ram_size)
  105. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  106. return 0;
  107. }
  108. #else
  109. int dram_init(void)
  110. {
  111. #ifndef CONFIG_TFABOOT
  112. static const struct fsl_mmdc_info mparam = {
  113. 0x05180000, /* mdctl */
  114. 0x00030035, /* mdpdc */
  115. 0x12554000, /* mdotc */
  116. 0xbabf7954, /* mdcfg0 */
  117. 0xdb328f64, /* mdcfg1 */
  118. 0x01ff00db, /* mdcfg2 */
  119. 0x00001680, /* mdmisc */
  120. 0x0f3c8000, /* mdref */
  121. 0x00002000, /* mdrwd */
  122. 0x00bf1023, /* mdor */
  123. 0x0000003f, /* mdasp */
  124. 0x0000022a, /* mpodtctrl */
  125. 0xa1390003, /* mpzqhwctrl */
  126. };
  127. mmdc_init(&mparam);
  128. #endif
  129. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  130. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  131. /* This will break-before-make MMU for DDR */
  132. update_early_mmu_table();
  133. #endif
  134. return 0;
  135. }
  136. #endif
  137. int board_early_init_f(void)
  138. {
  139. fsl_lsch2_early_init_f();
  140. return 0;
  141. }
  142. int board_init(void)
  143. {
  144. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  145. CONFIG_SYS_CCI400_OFFSET);
  146. /*
  147. * Set CCI-400 control override register to enable barrier
  148. * transaction
  149. */
  150. if (current_el() == 3)
  151. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  152. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  153. erratum_a010315();
  154. #endif
  155. #ifdef CONFIG_ENV_IS_NOWHERE
  156. gd->env_addr = (ulong)&default_environment[0];
  157. #endif
  158. #ifdef CONFIG_FSL_CAAM
  159. sec_init();
  160. #endif
  161. #ifdef CONFIG_FSL_LS_PPA
  162. ppa_init();
  163. #endif
  164. return 0;
  165. }
  166. #ifdef CONFIG_FSL_PFE
  167. void board_quiesce_devices(void)
  168. {
  169. pfe_command_stop(0, NULL);
  170. }
  171. #endif
  172. #ifdef CONFIG_TARGET_LS1012ARDB
  173. int esdhc_status_fixup(void *blob, const char *compat)
  174. {
  175. char esdhc1_path[] = "/soc/esdhc@1580000";
  176. bool sdhc2_en = false;
  177. u8 mux_sdhc2;
  178. u8 io = 0;
  179. int ret, bus_num = 0;
  180. #if CONFIG_IS_ENABLED(DM_I2C)
  181. struct udevice *dev;
  182. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
  183. 1, &dev);
  184. if (ret) {
  185. printf("%s: Cannot find udev for a bus %d\n", __func__,
  186. bus_num);
  187. return -ENXIO;
  188. }
  189. ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
  190. #else
  191. i2c_set_bus_num(bus_num);
  192. /* IO1[7:3] is the field of board revision info. */
  193. ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
  194. #endif
  195. if (ret < 0) {
  196. printf("Error reading i2c boot information!\n");
  197. return 0;
  198. }
  199. /* hwconfig method is used for RevD and later versions. */
  200. if ((io & SW_REV_MASK) <= SW_REV_D) {
  201. #ifdef CONFIG_HWCONFIG
  202. if (hwconfig("esdhc1"))
  203. sdhc2_en = true;
  204. #endif
  205. } else {
  206. /*
  207. * The I2C IO-expander for mux select is used to control
  208. * the muxing of various onboard interfaces.
  209. *
  210. * IO0[3:2] indicates SDHC2 interface demultiplexer
  211. * select lines.
  212. * 00 - SDIO wifi
  213. * 01 - GPIO (to Arduino)
  214. * 10 - eMMC Memory
  215. * 11 - SPI
  216. */
  217. #if CONFIG_IS_ENABLED(DM_I2C)
  218. ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
  219. #else
  220. ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
  221. #endif
  222. if (ret < 0) {
  223. printf("Error reading i2c boot information!\n");
  224. return 0;
  225. }
  226. mux_sdhc2 = (io & 0x0c) >> 2;
  227. /* Enable SDHC2 only when use SDIO wifi and eMMC */
  228. if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
  229. sdhc2_en = true;
  230. }
  231. if (sdhc2_en)
  232. do_fixup_by_path(blob, esdhc1_path, "status", "okay",
  233. sizeof("okay"), 1);
  234. else
  235. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  236. sizeof("disabled"), 1);
  237. return 0;
  238. }
  239. #endif
  240. int ft_board_setup(void *blob, struct bd_info *bd)
  241. {
  242. arch_fixup_fdt(blob);
  243. ft_cpu_setup(blob, bd);
  244. return 0;
  245. }
  246. static int switch_to_bank1(void)
  247. {
  248. u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
  249. int ret, bus_num = 0;
  250. #if CONFIG_IS_ENABLED(DM_I2C)
  251. struct udevice *dev;
  252. ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
  253. 1, &dev);
  254. if (ret) {
  255. printf("%s: Cannot find udev for a bus %d\n", __func__,
  256. bus_num);
  257. return -ENXIO;
  258. }
  259. /*
  260. * --------------------------------------------------------------------
  261. * |bus |I2C address| Device | Notes |
  262. * --------------------------------------------------------------------
  263. * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General |
  264. * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output|
  265. * | | | KW41GPIO) - NXP | (GPIO) expansion for the |
  266. * | | | PCAL9555AHF | I2C bus |
  267. * ----- --------------------------------------------------------------
  268. * - mount three IO expander(PCAL9555AHF) on I2C1
  269. *
  270. * PCAL9555A device address
  271. * slave address
  272. * --------------------------------------
  273. * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W |
  274. * --------------------------------------
  275. * | fixed | hardware selectable|
  276. *
  277. * Output port 1(Pinter register bits = 0x03)
  278. *
  279. * P1_[7~0] = 0xf4
  280. * P1_0 <---> CFG_MUX_QSPI_S0
  281. * P1_1 <---> CFG_MUX_QSPI_S1
  282. * CFG_MUX_QSPI_S[1:0] = 0b00
  283. *
  284. * QSPI chip-select demultiplexer select
  285. * ---------------------------------------------------------------------
  286. * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values
  287. * ---------------------------------------------------------------------
  288. * 0 | 0 |CS routed to SPI memory bank1(default)
  289. * ---------------------------------------------------------------------
  290. * 0 | 1 |CS routed to SPI memory bank2
  291. * ---------------------------------------------------------------------
  292. *
  293. */
  294. ret = dm_i2c_write(dev, offset_addr, &data, 1);
  295. #else /* Non DM I2C support - will be removed */
  296. i2c_set_bus_num(bus_num);
  297. ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
  298. #endif
  299. if (ret) {
  300. printf("i2c write error to chip : %u, addr : %u, data : %u\n",
  301. chip_addr, offset_addr, data);
  302. }
  303. return ret;
  304. }
  305. static int switch_to_bank2(void)
  306. {
  307. u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
  308. u8 chip_addr = 0x24;
  309. int ret, i, bus_num = 0;
  310. #if CONFIG_IS_ENABLED(DM_I2C)
  311. struct udevice *dev;
  312. ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
  313. 1, &dev);
  314. if (ret) {
  315. printf("%s: Cannot find udev for a bus %d\n", __func__,
  316. bus_num);
  317. return -ENXIO;
  318. }
  319. #else /* Non DM I2C support - will be removed */
  320. i2c_set_bus_num(bus_num);
  321. #endif
  322. /*
  323. * 1th step: config port 1
  324. * - the port 1 pin is enabled as an output
  325. * 2th step: output port 1
  326. * - P1_[7:0] output 0xf5,
  327. * then CFG_MUX_QSPI_S[1:0] equal to 0b01,
  328. * CS routed to SPI memory bank2
  329. */
  330. for (i = 0; i < sizeof(data); i++) {
  331. #if CONFIG_IS_ENABLED(DM_I2C)
  332. ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
  333. #else /* Non DM I2C support - will be removed */
  334. ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
  335. #endif
  336. if (ret) {
  337. printf("i2c write error to chip : %u, addr : %u, data : %u\n",
  338. chip_addr, offset_addr[i], data[i]);
  339. goto err;
  340. }
  341. }
  342. err:
  343. return ret;
  344. }
  345. static int convert_flash_bank(int bank)
  346. {
  347. int ret = 0;
  348. switch (bank) {
  349. case BOOT_FROM_UPPER_BANK:
  350. ret = switch_to_bank2();
  351. break;
  352. case BOOT_FROM_LOWER_BANK:
  353. ret = switch_to_bank1();
  354. break;
  355. default:
  356. ret = CMD_RET_USAGE;
  357. break;
  358. };
  359. return ret;
  360. }
  361. static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
  362. char *const argv[])
  363. {
  364. if (argc != 2)
  365. return CMD_RET_USAGE;
  366. if (strcmp(argv[1], "1") == 0)
  367. convert_flash_bank(BOOT_FROM_LOWER_BANK);
  368. else if (strcmp(argv[1], "2") == 0)
  369. convert_flash_bank(BOOT_FROM_UPPER_BANK);
  370. else
  371. return CMD_RET_USAGE;
  372. return 0;
  373. }
  374. U_BOOT_CMD(
  375. boot_bank, 2, 0, flash_bank_cmd,
  376. "Flash bank Selection Control",
  377. "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
  378. );