ls1012afrdm.c 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2018 NXP
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <i2c.h>
  8. #include <asm/cache.h>
  9. #include <init.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/fsl_serdes.h>
  14. #ifdef CONFIG_FSL_LS_PPA
  15. #include <asm/arch/ppa.h>
  16. #endif
  17. #include <asm/arch/mmu.h>
  18. #include <asm/arch/soc.h>
  19. #include <fsl_esdhc.h>
  20. #include <hwconfig.h>
  21. #include <env_internal.h>
  22. #include <fsl_mmdc.h>
  23. #include <netdev.h>
  24. #include <fsl_sec.h>
  25. #include <net/pfe_eth/pfe/pfe_hw.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. static inline int get_board_version(void)
  28. {
  29. uint32_t val;
  30. #ifdef CONFIG_TARGET_LS1012AFRDM
  31. val = 0;
  32. #else
  33. struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
  34. val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
  35. #endif
  36. return val;
  37. }
  38. int checkboard(void)
  39. {
  40. #ifdef CONFIG_TARGET_LS1012AFRDM
  41. puts("Board: LS1012AFRDM ");
  42. #else
  43. int rev;
  44. rev = get_board_version();
  45. puts("Board: FRWY-LS1012A ");
  46. puts("Version");
  47. switch (rev) {
  48. case BOARD_REV_A_B:
  49. puts(": RevA/B ");
  50. break;
  51. case BOARD_REV_C:
  52. puts(": RevC ");
  53. break;
  54. default:
  55. puts(": unknown");
  56. break;
  57. }
  58. #endif
  59. return 0;
  60. }
  61. #ifdef CONFIG_TARGET_LS1012AFRWY
  62. int esdhc_status_fixup(void *blob, const char *compat)
  63. {
  64. char esdhc0_path[] = "/soc/esdhc@1560000";
  65. char esdhc1_path[] = "/soc/esdhc@1580000";
  66. do_fixup_by_path(blob, esdhc0_path, "status", "okay",
  67. sizeof("okay"), 1);
  68. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  69. sizeof("disabled"), 1);
  70. return 0;
  71. }
  72. #endif
  73. #ifdef CONFIG_TFABOOT
  74. int dram_init(void)
  75. {
  76. #ifdef CONFIG_TARGET_LS1012AFRWY
  77. int board_rev;
  78. #endif
  79. gd->ram_size = tfa_get_dram_size();
  80. if (!gd->ram_size) {
  81. #ifdef CONFIG_TARGET_LS1012AFRWY
  82. board_rev = get_board_version();
  83. if (board_rev & BOARD_REV_C)
  84. gd->ram_size = SYS_SDRAM_SIZE_1024;
  85. else
  86. gd->ram_size = SYS_SDRAM_SIZE_512;
  87. #else
  88. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  89. #endif
  90. }
  91. return 0;
  92. }
  93. #else
  94. int dram_init(void)
  95. {
  96. #ifdef CONFIG_TARGET_LS1012AFRWY
  97. int board_rev;
  98. #endif
  99. struct fsl_mmdc_info mparam = {
  100. 0x04180000, /* mdctl */
  101. 0x00030035, /* mdpdc */
  102. 0x12554000, /* mdotc */
  103. 0xbabf7954, /* mdcfg0 */
  104. 0xdb328f64, /* mdcfg1 */
  105. 0x01ff00db, /* mdcfg2 */
  106. 0x00001680, /* mdmisc */
  107. 0x0f3c8000, /* mdref */
  108. 0x00002000, /* mdrwd */
  109. 0x00bf1023, /* mdor */
  110. 0x0000003f, /* mdasp */
  111. 0x0000022a, /* mpodtctrl */
  112. 0xa1390003, /* mpzqhwctrl */
  113. };
  114. #ifdef CONFIG_TARGET_LS1012AFRWY
  115. board_rev = get_board_version();
  116. if (board_rev == BOARD_REV_C) {
  117. mparam.mdctl = 0x05180000;
  118. gd->ram_size = SYS_SDRAM_SIZE_1024;
  119. } else {
  120. gd->ram_size = SYS_SDRAM_SIZE_512;
  121. }
  122. #else
  123. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  124. #endif
  125. mmdc_init(&mparam);
  126. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  127. /* This will break-before-make MMU for DDR */
  128. update_early_mmu_table();
  129. #endif
  130. return 0;
  131. }
  132. #endif
  133. int board_early_init_f(void)
  134. {
  135. fsl_lsch2_early_init_f();
  136. return 0;
  137. }
  138. int board_init(void)
  139. {
  140. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  141. CONFIG_SYS_CCI400_OFFSET);
  142. /*
  143. * Set CCI-400 control override register to enable barrier
  144. * transaction
  145. */
  146. if (current_el() == 3)
  147. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  148. #ifdef CONFIG_ENV_IS_NOWHERE
  149. gd->env_addr = (ulong)&default_environment[0];
  150. #endif
  151. #ifdef CONFIG_FSL_CAAM
  152. sec_init();
  153. #endif
  154. #ifdef CONFIG_FSL_LS_PPA
  155. ppa_init();
  156. #endif
  157. return 0;
  158. }
  159. #ifdef CONFIG_FSL_PFE
  160. void board_quiesce_devices(void)
  161. {
  162. pfe_command_stop(0, NULL);
  163. }
  164. #endif
  165. int ft_board_setup(void *blob, struct bd_info *bd)
  166. {
  167. arch_fixup_fdt(blob);
  168. ft_cpu_setup(blob, bd);
  169. return 0;
  170. }