imx8mp_evk.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <errno.h>
  8. #include <init.h>
  9. #include <miiphy.h>
  10. #include <netdev.h>
  11. #include <linux/delay.h>
  12. #include <asm/global_data.h>
  13. #include <asm/mach-imx/iomux-v3.h>
  14. #include <asm-generic/gpio.h>
  15. #include <asm/arch/imx8mp_pins.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/mach-imx/gpio.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  21. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  22. static iomux_v3_cfg_t const uart_pads[] = {
  23. MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  24. MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  25. };
  26. static iomux_v3_cfg_t const wdog_pads[] = {
  27. MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  28. };
  29. int board_early_init_f(void)
  30. {
  31. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  32. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  33. set_wdog_reset(wdog);
  34. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  35. return 0;
  36. }
  37. static void setup_fec(void)
  38. {
  39. struct iomuxc_gpr_base_regs *gpr =
  40. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  41. /* Enable RGMII TX clk output */
  42. setbits_le32(&gpr->gpr[1], BIT(22));
  43. }
  44. #define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
  45. static iomux_v3_cfg_t const eqos_rst_pads[] = {
  46. MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  47. };
  48. static void setup_iomux_eqos(void)
  49. {
  50. imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
  51. ARRAY_SIZE(eqos_rst_pads));
  52. gpio_request(EQOS_RST_PAD, "eqos_rst");
  53. gpio_direction_output(EQOS_RST_PAD, 0);
  54. mdelay(15);
  55. gpio_direction_output(EQOS_RST_PAD, 1);
  56. mdelay(100);
  57. }
  58. static int setup_eqos(void)
  59. {
  60. struct iomuxc_gpr_base_regs *gpr =
  61. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  62. setup_iomux_eqos();
  63. /* set INTF as RGMII, enable RGMII TXC clock */
  64. clrsetbits_le32(&gpr->gpr[1],
  65. IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
  66. setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
  67. return set_clk_eqos(ENET_125MHZ);
  68. }
  69. #if CONFIG_IS_ENABLED(NET)
  70. int board_phy_config(struct phy_device *phydev)
  71. {
  72. if (phydev->drv->config)
  73. phydev->drv->config(phydev);
  74. return 0;
  75. }
  76. #endif
  77. int board_init(void)
  78. {
  79. int ret = 0;
  80. if (CONFIG_IS_ENABLED(FEC_MXC)) {
  81. setup_fec();
  82. if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
  83. ret = setup_eqos();
  84. }
  85. return ret;
  86. }
  87. int board_late_init(void)
  88. {
  89. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  90. env_set("board_name", "EVK");
  91. env_set("board_rev", "iMX8MP");
  92. #endif
  93. return 0;
  94. }