spl.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Amarula Solutions B.V.
  4. * Copyright (C) 2016 Engicam S.r.l.
  5. * Author: Jagan Teki <jagan@amarulasolutions.com>
  6. */
  7. #include <common.h>
  8. #include <image.h>
  9. #include <init.h>
  10. #include <serial.h>
  11. #include <spl.h>
  12. #include <linux/delay.h>
  13. #include <asm/io.h>
  14. #include <asm/gpio.h>
  15. #include <linux/sizes.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/crm_regs.h>
  18. #include <asm/arch/iomux.h>
  19. #include <asm/arch/mx6-ddr.h>
  20. #include <asm/arch/mx6-pins.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/mach-imx/iomux-v3.h>
  23. #include <asm/mach-imx/video.h>
  24. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  25. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  26. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  27. static iomux_v3_cfg_t const uart_pads[] = {
  28. #ifdef CONFIG_MX6QDL
  29. IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  30. IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  31. #elif CONFIG_MX6UL
  32. IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
  33. IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
  34. #endif
  35. };
  36. #ifdef CONFIG_SPL_LOAD_FIT
  37. int board_fit_config_name_match(const char *name)
  38. {
  39. if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
  40. return 0;
  41. else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
  42. return 0;
  43. else if (is_mx6dq() && !strcmp(name, "imx6q-icore-mipi"))
  44. return 0;
  45. else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
  46. return 0;
  47. else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
  48. return 0;
  49. else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-mipi"))
  50. return 0;
  51. else
  52. return -1;
  53. }
  54. #endif
  55. #ifdef CONFIG_ENV_IS_IN_MMC
  56. void board_boot_order(u32 *spl_boot_list)
  57. {
  58. u32 bmode = imx6_src_get_boot_mode();
  59. u8 boot_dev = BOOT_DEVICE_MMC1;
  60. switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
  61. case IMX6_BMODE_SD:
  62. case IMX6_BMODE_ESD:
  63. /* SD/eSD - BOOT_DEVICE_MMC1 */
  64. break;
  65. case IMX6_BMODE_MMC:
  66. case IMX6_BMODE_EMMC:
  67. /* MMC/eMMC */
  68. boot_dev = BOOT_DEVICE_MMC2;
  69. break;
  70. default:
  71. /* Default - BOOT_DEVICE_MMC1 */
  72. printf("Wrong board boot order\n");
  73. break;
  74. }
  75. spl_boot_list[0] = boot_dev;
  76. }
  77. #endif
  78. #ifdef CONFIG_SPL_OS_BOOT
  79. int spl_start_uboot(void)
  80. {
  81. /* break into full u-boot on 'c' */
  82. if (serial_tstc() && serial_getc() == 'c')
  83. return 1;
  84. return 0;
  85. }
  86. #endif
  87. #ifdef CONFIG_MX6QDL
  88. /*
  89. * Driving strength:
  90. * 0x30 == 40 Ohm
  91. * 0x28 == 48 Ohm
  92. */
  93. #define IMX6DQ_DRIVE_STRENGTH 0x30
  94. #define IMX6SDL_DRIVE_STRENGTH 0x28
  95. /* configure MX6Q/DUAL mmdc DDR io registers */
  96. static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  97. .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  98. .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  99. .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  100. .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  101. .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  102. .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  103. .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  104. .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  105. .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  106. .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  107. .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  108. .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  109. .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  110. .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  111. .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  112. .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  113. .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  114. .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  115. .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  116. .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  117. .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  118. .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  119. .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  120. .dram_sdba2 = 0x00000000,
  121. .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  122. .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  123. };
  124. /* configure MX6Q/DUAL mmdc GRP io registers */
  125. static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  126. .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  127. .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  128. .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  129. .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  130. .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  131. .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  132. .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  133. .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  134. .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  135. .grp_ddrmode_ctl = 0x00020000,
  136. .grp_ddrpke = 0x00000000,
  137. .grp_ddrmode = 0x00020000,
  138. .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  139. .grp_ddr_type = 0x000c0000,
  140. };
  141. /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  142. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  143. .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  144. .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  145. .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  146. .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  147. .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  148. .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  149. .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  150. .dram_sdba2 = 0x00000000,
  151. .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  152. .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  153. .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  154. .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  155. .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  156. .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  157. .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  158. .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  159. .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  160. .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  161. .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  162. .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  163. .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  164. .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  165. .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  166. .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  167. .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  168. .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  169. };
  170. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  171. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  172. .grp_ddr_type = 0x000c0000,
  173. .grp_ddrmode_ctl = 0x00020000,
  174. .grp_ddrpke = 0x00000000,
  175. .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  176. .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  177. .grp_ddrmode = 0x00020000,
  178. .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  179. .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  180. .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  181. .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  182. .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  183. .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  184. .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  185. .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  186. };
  187. /* mt41j256 */
  188. static struct mx6_ddr3_cfg mt41j256 = {
  189. .mem_speed = 1066,
  190. .density = 2,
  191. .width = 16,
  192. .banks = 8,
  193. .rowaddr = 13,
  194. .coladdr = 10,
  195. .pagesz = 2,
  196. .trcd = 1375,
  197. .trcmin = 4875,
  198. .trasmin = 3500,
  199. .SRT = 0,
  200. };
  201. static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
  202. .p0_mpwldectrl0 = 0x000E0009,
  203. .p0_mpwldectrl1 = 0x0018000E,
  204. .p1_mpwldectrl0 = 0x00000007,
  205. .p1_mpwldectrl1 = 0x00000000,
  206. .p0_mpdgctrl0 = 0x43280334,
  207. .p0_mpdgctrl1 = 0x031C0314,
  208. .p1_mpdgctrl0 = 0x4318031C,
  209. .p1_mpdgctrl1 = 0x030C0258,
  210. .p0_mprddlctl = 0x3E343A40,
  211. .p1_mprddlctl = 0x383C3844,
  212. .p0_mpwrdlctl = 0x40404440,
  213. .p1_mpwrdlctl = 0x4C3E4446,
  214. };
  215. /* DDR 64bit */
  216. static struct mx6_ddr_sysinfo mem_q = {
  217. .ddr_type = DDR_TYPE_DDR3,
  218. .dsize = 2,
  219. .cs1_mirror = 0,
  220. /* config for full 4GB range so that get_mem_size() works */
  221. .cs_density = 32,
  222. .ncs = 1,
  223. .bi_on = 1,
  224. .rtt_nom = 2,
  225. .rtt_wr = 2,
  226. .ralat = 5,
  227. .walat = 0,
  228. .mif3_mode = 3,
  229. .rst_to_cke = 0x23,
  230. .sde_to_rst = 0x10,
  231. };
  232. static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
  233. .p0_mpwldectrl0 = 0x001F0024,
  234. .p0_mpwldectrl1 = 0x00110018,
  235. .p1_mpwldectrl0 = 0x001F0024,
  236. .p1_mpwldectrl1 = 0x00110018,
  237. .p0_mpdgctrl0 = 0x4230022C,
  238. .p0_mpdgctrl1 = 0x02180220,
  239. .p1_mpdgctrl0 = 0x42440248,
  240. .p1_mpdgctrl1 = 0x02300238,
  241. .p0_mprddlctl = 0x44444A48,
  242. .p1_mprddlctl = 0x46484A42,
  243. .p0_mpwrdlctl = 0x38383234,
  244. .p1_mpwrdlctl = 0x3C34362E,
  245. };
  246. /* DDR 64bit 1GB */
  247. static struct mx6_ddr_sysinfo mem_dl = {
  248. .dsize = 2,
  249. .cs1_mirror = 0,
  250. /* config for full 4GB range so that get_mem_size() works */
  251. .cs_density = 32,
  252. .ncs = 1,
  253. .bi_on = 1,
  254. .rtt_nom = 1,
  255. .rtt_wr = 1,
  256. .ralat = 5,
  257. .walat = 0,
  258. .mif3_mode = 3,
  259. .rst_to_cke = 0x23,
  260. .sde_to_rst = 0x10,
  261. };
  262. /* DDR 32bit 512MB */
  263. static struct mx6_ddr_sysinfo mem_s = {
  264. .dsize = 1,
  265. .cs1_mirror = 0,
  266. /* config for full 4GB range so that get_mem_size() works */
  267. .cs_density = 32,
  268. .ncs = 1,
  269. .bi_on = 1,
  270. .rtt_nom = 1,
  271. .rtt_wr = 1,
  272. .ralat = 5,
  273. .walat = 0,
  274. .mif3_mode = 3,
  275. .rst_to_cke = 0x23,
  276. .sde_to_rst = 0x10,
  277. };
  278. #endif /* CONFIG_MX6QDL */
  279. #ifdef CONFIG_MX6UL
  280. static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  281. .grp_addds = 0x00000030,
  282. .grp_ddrmode_ctl = 0x00020000,
  283. .grp_b0ds = 0x00000030,
  284. .grp_ctlds = 0x00000030,
  285. .grp_b1ds = 0x00000030,
  286. .grp_ddrpke = 0x00000000,
  287. .grp_ddrmode = 0x00020000,
  288. .grp_ddr_type = 0x000c0000,
  289. };
  290. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  291. .dram_dqm0 = 0x00000030,
  292. .dram_dqm1 = 0x00000030,
  293. .dram_ras = 0x00000030,
  294. .dram_cas = 0x00000030,
  295. .dram_odt0 = 0x00000030,
  296. .dram_odt1 = 0x00000030,
  297. .dram_sdba2 = 0x00000000,
  298. .dram_sdclk_0 = 0x00000008,
  299. .dram_sdqs0 = 0x00000038,
  300. .dram_sdqs1 = 0x00000030,
  301. .dram_reset = 0x00000030,
  302. };
  303. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  304. .p0_mpwldectrl0 = 0x00070007,
  305. .p0_mpdgctrl0 = 0x41490145,
  306. .p0_mprddlctl = 0x40404546,
  307. .p0_mpwrdlctl = 0x4040524D,
  308. };
  309. struct mx6_ddr_sysinfo ddr_sysinfo = {
  310. .dsize = 0,
  311. .cs_density = 20,
  312. .ncs = 1,
  313. .cs1_mirror = 0,
  314. .rtt_wr = 2,
  315. .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
  316. .walat = 1, /* Write additional latency */
  317. .ralat = 5, /* Read additional latency */
  318. .mif3_mode = 3, /* Command prediction working mode */
  319. .bi_on = 1, /* Bank interleaving enabled */
  320. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  321. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  322. .ddr_type = DDR_TYPE_DDR3,
  323. };
  324. static struct mx6_ddr3_cfg mem_ddr = {
  325. .mem_speed = 800,
  326. .density = 4,
  327. .width = 16,
  328. .banks = 8,
  329. #ifdef TARGET_MX6UL_ISIOT
  330. .rowaddr = 15,
  331. #else
  332. .rowaddr = 13,
  333. #endif
  334. .coladdr = 10,
  335. .pagesz = 2,
  336. .trcd = 1375,
  337. .trcmin = 4875,
  338. .trasmin = 3500,
  339. };
  340. #endif /* CONFIG_MX6UL */
  341. static void ccgr_init(void)
  342. {
  343. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  344. #ifdef CONFIG_MX6QDL
  345. writel(0x00003F3F, &ccm->CCGR0);
  346. writel(0x0030FC00, &ccm->CCGR1);
  347. writel(0x000FC000, &ccm->CCGR2);
  348. writel(0x3F300000, &ccm->CCGR3);
  349. writel(0xFF00F300, &ccm->CCGR4);
  350. writel(0x0F0000C3, &ccm->CCGR5);
  351. writel(0x000003CC, &ccm->CCGR6);
  352. #elif CONFIG_MX6UL
  353. writel(0x00c03f3f, &ccm->CCGR0);
  354. writel(0xfcffff00, &ccm->CCGR1);
  355. writel(0x0cffffcc, &ccm->CCGR2);
  356. writel(0x3f3c3030, &ccm->CCGR3);
  357. writel(0xff00fffc, &ccm->CCGR4);
  358. writel(0x033f30ff, &ccm->CCGR5);
  359. writel(0x00c00fff, &ccm->CCGR6);
  360. #endif
  361. }
  362. static void spl_dram_init(void)
  363. {
  364. #ifdef CONFIG_MX6QDL
  365. if (is_mx6solo()) {
  366. mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  367. mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
  368. } else if (is_mx6dl()) {
  369. mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  370. mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
  371. } else if (is_mx6dq()) {
  372. mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
  373. mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
  374. }
  375. #elif CONFIG_MX6UL
  376. mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  377. mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  378. #endif
  379. udelay(100);
  380. }
  381. void board_init_f(ulong dummy)
  382. {
  383. ccgr_init();
  384. /* setup AIPS and disable watchdog */
  385. arch_cpu_init();
  386. if (!(is_mx6ul()))
  387. gpr_init();
  388. /* iomux */
  389. SETUP_IOMUX_PADS(uart_pads);
  390. /* setup GP timer */
  391. timer_init();
  392. /* UART clocks enabled and gd valid - init serial console */
  393. preloader_console_init();
  394. /* DDR initialization */
  395. spl_dram_init();
  396. }