dh_imx6_spl.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * DHCOM DH-iMX6 PDK SPL support
  4. *
  5. * Copyright (C) 2017 Marek Vasut <marex@denx.de>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/iomux.h>
  13. #include <asm/arch/mx6-ddr.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <asm/mach-imx/iomux-v3.h>
  19. #include <asm/mach-imx/mxc_i2c.h>
  20. #include <asm/io.h>
  21. #include <errno.h>
  22. #include <fuse.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <i2c.h>
  25. #include <mmc.h>
  26. #include <spl.h>
  27. #include <linux/delay.h>
  28. #define ENET_PAD_CTRL \
  29. (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  30. PAD_CTL_HYS)
  31. #define GPIO_PAD_CTRL \
  32. (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  33. #define SPI_PAD_CTRL \
  34. (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  35. PAD_CTL_SRE_FAST)
  36. #define UART_PAD_CTRL \
  37. (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  38. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  39. #define USDHC_PAD_CTRL \
  40. (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  41. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  42. static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
  43. .dram_sdclk_0 = 0x00020030,
  44. .dram_sdclk_1 = 0x00020030,
  45. .dram_cas = 0x00020030,
  46. .dram_ras = 0x00020030,
  47. .dram_reset = 0x00020030,
  48. .dram_sdcke0 = 0x00003000,
  49. .dram_sdcke1 = 0x00003000,
  50. .dram_sdba2 = 0x00000000,
  51. .dram_sdodt0 = 0x00003030,
  52. .dram_sdodt1 = 0x00003030,
  53. .dram_sdqs0 = 0x00000030,
  54. .dram_sdqs1 = 0x00000030,
  55. .dram_sdqs2 = 0x00000030,
  56. .dram_sdqs3 = 0x00000030,
  57. .dram_sdqs4 = 0x00000030,
  58. .dram_sdqs5 = 0x00000030,
  59. .dram_sdqs6 = 0x00000030,
  60. .dram_sdqs7 = 0x00000030,
  61. .dram_dqm0 = 0x00020030,
  62. .dram_dqm1 = 0x00020030,
  63. .dram_dqm2 = 0x00020030,
  64. .dram_dqm3 = 0x00020030,
  65. .dram_dqm4 = 0x00020030,
  66. .dram_dqm5 = 0x00020030,
  67. .dram_dqm6 = 0x00020030,
  68. .dram_dqm7 = 0x00020030,
  69. };
  70. static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
  71. .grp_ddr_type = 0x000C0000,
  72. .grp_ddrmode_ctl = 0x00020000,
  73. .grp_ddrpke = 0x00000000,
  74. .grp_addds = 0x00000030,
  75. .grp_ctlds = 0x00000030,
  76. .grp_ddrmode = 0x00020000,
  77. .grp_b0ds = 0x00000030,
  78. .grp_b1ds = 0x00000030,
  79. .grp_b2ds = 0x00000030,
  80. .grp_b3ds = 0x00000030,
  81. .grp_b4ds = 0x00000030,
  82. .grp_b5ds = 0x00000030,
  83. .grp_b6ds = 0x00000030,
  84. .grp_b7ds = 0x00000030,
  85. };
  86. static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
  87. .dram_sdclk_0 = 0x00020030,
  88. .dram_sdclk_1 = 0x00020030,
  89. .dram_cas = 0x00020030,
  90. .dram_ras = 0x00020030,
  91. .dram_reset = 0x00020030,
  92. .dram_sdcke0 = 0x00003000,
  93. .dram_sdcke1 = 0x00003000,
  94. .dram_sdba2 = 0x00000000,
  95. .dram_sdodt0 = 0x00003030,
  96. .dram_sdodt1 = 0x00003030,
  97. .dram_sdqs0 = 0x00000030,
  98. .dram_sdqs1 = 0x00000030,
  99. .dram_sdqs2 = 0x00000030,
  100. .dram_sdqs3 = 0x00000030,
  101. .dram_sdqs4 = 0x00000030,
  102. .dram_sdqs5 = 0x00000030,
  103. .dram_sdqs6 = 0x00000030,
  104. .dram_sdqs7 = 0x00000030,
  105. .dram_dqm0 = 0x00020030,
  106. .dram_dqm1 = 0x00020030,
  107. .dram_dqm2 = 0x00020030,
  108. .dram_dqm3 = 0x00020030,
  109. .dram_dqm4 = 0x00020030,
  110. .dram_dqm5 = 0x00020030,
  111. .dram_dqm6 = 0x00020030,
  112. .dram_dqm7 = 0x00020030,
  113. };
  114. static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
  115. .grp_ddr_type = 0x000C0000,
  116. .grp_ddrmode_ctl = 0x00020000,
  117. .grp_ddrpke = 0x00000000,
  118. .grp_addds = 0x00000030,
  119. .grp_ctlds = 0x00000030,
  120. .grp_ddrmode = 0x00020000,
  121. .grp_b0ds = 0x00000030,
  122. .grp_b1ds = 0x00000030,
  123. .grp_b2ds = 0x00000030,
  124. .grp_b3ds = 0x00000030,
  125. .grp_b4ds = 0x00000030,
  126. .grp_b5ds = 0x00000030,
  127. .grp_b6ds = 0x00000030,
  128. .grp_b7ds = 0x00000030,
  129. };
  130. static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
  131. .p0_mpwldectrl0 = 0x00150019,
  132. .p0_mpwldectrl1 = 0x001C000B,
  133. .p1_mpwldectrl0 = 0x00020018,
  134. .p1_mpwldectrl1 = 0x0002000C,
  135. .p0_mpdgctrl0 = 0x43140320,
  136. .p0_mpdgctrl1 = 0x03080304,
  137. .p1_mpdgctrl0 = 0x43180320,
  138. .p1_mpdgctrl1 = 0x03100254,
  139. .p0_mprddlctl = 0x4830383C,
  140. .p1_mprddlctl = 0x3836323E,
  141. .p0_mpwrdlctl = 0x3E444642,
  142. .p1_mpwrdlctl = 0x42344442,
  143. };
  144. static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
  145. .p0_mpwldectrl0 = 0x0040003C,
  146. .p0_mpwldectrl1 = 0x0032003E,
  147. .p0_mpdgctrl0 = 0x42350231,
  148. .p0_mpdgctrl1 = 0x021A0218,
  149. .p0_mprddlctl = 0x4B4B4E49,
  150. .p0_mpwrdlctl = 0x3F3F3035,
  151. };
  152. static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
  153. .p0_mpwldectrl0 = 0x001a001a,
  154. .p0_mpwldectrl1 = 0x00260015,
  155. .p0_mpdgctrl0 = 0x030c0320,
  156. .p0_mpdgctrl1 = 0x03100304,
  157. .p0_mprddlctl = 0x432e3538,
  158. .p0_mpwrdlctl = 0x363f423d,
  159. .p1_mpwldectrl0 = 0x0006001e,
  160. .p1_mpwldectrl1 = 0x00050015,
  161. .p1_mpdgctrl0 = 0x031c0324,
  162. .p1_mpdgctrl1 = 0x030c0258,
  163. .p1_mprddlctl = 0x3834313f,
  164. .p1_mpwrdlctl = 0x47374a42,
  165. };
  166. static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
  167. .p0_mpwldectrl0 = 0x003A003A,
  168. .p0_mpwldectrl1 = 0x0030002F,
  169. .p1_mpwldectrl0 = 0x002F0038,
  170. .p1_mpwldectrl1 = 0x00270039,
  171. .p0_mpdgctrl0 = 0x420F020F,
  172. .p0_mpdgctrl1 = 0x01760175,
  173. .p1_mpdgctrl0 = 0x41640171,
  174. .p1_mpdgctrl1 = 0x015E0160,
  175. .p0_mprddlctl = 0x45464B4A,
  176. .p1_mprddlctl = 0x49484A46,
  177. .p0_mpwrdlctl = 0x40402E32,
  178. .p1_mpwrdlctl = 0x3A3A3231,
  179. };
  180. static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
  181. .p0_mpwldectrl0 = 0x0040003C,
  182. .p0_mpwldectrl1 = 0x0032003E,
  183. .p0_mpdgctrl0 = 0x42350231,
  184. .p0_mpdgctrl1 = 0x021A0218,
  185. .p0_mprddlctl = 0x4B4B4E49,
  186. .p0_mpwrdlctl = 0x3F3F3035,
  187. };
  188. /*
  189. * 2 Gbit DDR3 memory
  190. * - NANYA #NT5CC128M16IP-DII
  191. * - NANYA #NT5CB128M16FP-DII
  192. */
  193. static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
  194. .mem_speed = 1600,
  195. .density = 2,
  196. .width = 16,
  197. .banks = 8,
  198. .rowaddr = 14,
  199. .coladdr = 10,
  200. .pagesz = 2,
  201. .trcd = 1375,
  202. .trcmin = 5863,
  203. .trasmin = 3750,
  204. };
  205. /*
  206. * 4 Gbit DDR3 memory
  207. * - Intelligent Memory #IM4G16D3EABG-125I
  208. */
  209. static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
  210. .mem_speed = 1600,
  211. .density = 4,
  212. .width = 16,
  213. .banks = 8,
  214. .rowaddr = 15,
  215. .coladdr = 10,
  216. .pagesz = 2,
  217. .trcd = 1375,
  218. .trcmin = 4875,
  219. .trasmin = 3500,
  220. };
  221. /* DDR3 64bit */
  222. static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
  223. /* width of data bus:0=16,1=32,2=64 */
  224. .dsize = 2,
  225. .cs_density = 32,
  226. .ncs = 1, /* single chip select */
  227. .cs1_mirror = 1,
  228. .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
  229. .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
  230. .walat = 1, /* Write additional latency */
  231. .ralat = 5, /* Read additional latency */
  232. .mif3_mode = 3, /* Command prediction working mode */
  233. .bi_on = 1, /* Bank interleaving enabled */
  234. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  235. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  236. .refsel = 1, /* Refresh cycles at 32KHz */
  237. .refr = 3, /* 4 refresh commands per refresh cycle */
  238. };
  239. /* DDR3 32bit */
  240. static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
  241. /* width of data bus:0=16,1=32,2=64 */
  242. .dsize = 1,
  243. .cs_density = 32,
  244. .ncs = 1, /* single chip select */
  245. .cs1_mirror = 1,
  246. .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
  247. .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
  248. .walat = 1, /* Write additional latency */
  249. .ralat = 5, /* Read additional latency */
  250. .mif3_mode = 3, /* Command prediction working mode */
  251. .bi_on = 1, /* Bank interleaving enabled */
  252. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  253. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  254. .refsel = 1, /* Refresh cycles at 32KHz */
  255. .refr = 3, /* 4 refresh commands per refresh cycle */
  256. };
  257. static void ccgr_init(void)
  258. {
  259. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  260. writel(0x00C03F3F, &ccm->CCGR0);
  261. writel(0x0030FC03, &ccm->CCGR1);
  262. writel(0x0FFFC000, &ccm->CCGR2);
  263. writel(0x3FF00000, &ccm->CCGR3);
  264. writel(0x00FFF300, &ccm->CCGR4);
  265. writel(0x0F0000C3, &ccm->CCGR5);
  266. writel(0x000003FF, &ccm->CCGR6);
  267. }
  268. /* Board ID */
  269. static iomux_v3_cfg_t const hwcode_pads[] = {
  270. IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  271. IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  272. IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  273. };
  274. static void setup_iomux_boardid(void)
  275. {
  276. /* HW code pins: Setup alternate function and configure pads */
  277. SETUP_IOMUX_PADS(hwcode_pads);
  278. }
  279. /* DDR Code */
  280. static iomux_v3_cfg_t const ddrcode_pads[] = {
  281. IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  282. IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  283. };
  284. static void setup_iomux_ddrcode(void)
  285. {
  286. /* ddr code pins */
  287. SETUP_IOMUX_PADS(ddrcode_pads);
  288. }
  289. enum dhcom_ddr3_code {
  290. DH_DDR3_SIZE_256MIB = 0x00,
  291. DH_DDR3_SIZE_512MIB = 0x01,
  292. DH_DDR3_SIZE_1GIB = 0x02,
  293. DH_DDR3_SIZE_2GIB = 0x03
  294. };
  295. #define DDR3_CODE_BIT_0 IMX_GPIO_NR(2, 22)
  296. #define DDR3_CODE_BIT_1 IMX_GPIO_NR(2, 21)
  297. enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
  298. {
  299. enum dhcom_ddr3_code ddr3_code;
  300. gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
  301. gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
  302. gpio_direction_input(DDR3_CODE_BIT_0);
  303. gpio_direction_input(DDR3_CODE_BIT_1);
  304. /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
  305. ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
  306. | (!!gpio_get_value(DDR3_CODE_BIT_0));
  307. return ddr3_code;
  308. }
  309. /* GPIO */
  310. static iomux_v3_cfg_t const gpio_pads[] = {
  311. IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  312. IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  313. IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  314. IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  315. IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  316. IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  317. IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  318. IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  319. IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  320. IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  321. IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  322. IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  323. IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  324. IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  325. IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  326. IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  327. IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  328. IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  329. IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  330. IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  331. IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  332. IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  333. IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  334. };
  335. static void setup_iomux_gpio(void)
  336. {
  337. SETUP_IOMUX_PADS(gpio_pads);
  338. }
  339. /* Ethernet */
  340. static iomux_v3_cfg_t const enet_pads[] = {
  341. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  342. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  343. IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  344. IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  345. IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  346. IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  347. IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  348. IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  349. IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  350. IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  351. /* SMSC PHY Reset */
  352. IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  353. /* ENET_VIO_GPIO */
  354. IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  355. /* ENET_Interrupt - (not used) */
  356. IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  357. };
  358. static void setup_iomux_enet(void)
  359. {
  360. SETUP_IOMUX_PADS(enet_pads);
  361. }
  362. /* SD interface */
  363. static iomux_v3_cfg_t const usdhc2_pads[] = {
  364. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  365. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  366. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  367. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  368. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  369. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  370. IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
  371. };
  372. /* onboard microSD */
  373. static iomux_v3_cfg_t const usdhc3_pads[] = {
  374. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  375. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  376. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  377. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  378. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  379. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  380. IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
  381. };
  382. /* eMMC */
  383. static iomux_v3_cfg_t const usdhc4_pads[] = {
  384. IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  385. IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  386. IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  387. IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  388. IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  389. IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  390. IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  391. IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  392. IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  393. IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  394. };
  395. /* SD */
  396. static void setup_iomux_sd(void)
  397. {
  398. SETUP_IOMUX_PADS(usdhc2_pads);
  399. SETUP_IOMUX_PADS(usdhc3_pads);
  400. SETUP_IOMUX_PADS(usdhc4_pads);
  401. }
  402. /* SPI */
  403. static iomux_v3_cfg_t const ecspi1_pads[] = {
  404. /* SS0 - SS of boot flash */
  405. IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 |
  406. MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
  407. /* SS2 - SS of DHCOM SPI1 */
  408. IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 |
  409. MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
  410. IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  411. IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  412. IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  413. };
  414. static void setup_iomux_spi(void)
  415. {
  416. SETUP_IOMUX_PADS(ecspi1_pads);
  417. }
  418. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  419. {
  420. if (bus == 0 && cs == 0)
  421. return IMX_GPIO_NR(2, 30);
  422. else
  423. return -1;
  424. }
  425. /* UART */
  426. static iomux_v3_cfg_t const uart1_pads[] = {
  427. IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  428. IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  429. };
  430. static void setup_iomux_uart(void)
  431. {
  432. SETUP_IOMUX_PADS(uart1_pads);
  433. }
  434. #ifdef CONFIG_FSL_USDHC
  435. struct fsl_esdhc_cfg usdhc_cfg[1] = {
  436. {USDHC4_BASE_ADDR},
  437. };
  438. int board_mmc_get_env_dev(int devno)
  439. {
  440. return devno - 1;
  441. }
  442. int board_mmc_getcd(struct mmc *mmc)
  443. {
  444. return 1; /* eMMC/uSDHC4 is always present */
  445. }
  446. int board_mmc_init(struct bd_info *bis)
  447. {
  448. SETUP_IOMUX_PADS(usdhc4_pads);
  449. usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
  450. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  451. usdhc_cfg[0].max_bus_width = 8;
  452. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  453. }
  454. #endif
  455. /* USB */
  456. static iomux_v3_cfg_t const usb_pads[] = {
  457. IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
  458. IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  459. };
  460. static void setup_iomux_usb(void)
  461. {
  462. SETUP_IOMUX_PADS(usb_pads);
  463. }
  464. /* Perform DDR DRAM calibration */
  465. static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
  466. {
  467. int ret = 0;
  468. #ifdef CONFIG_MX6_DDRCAL
  469. udelay(100);
  470. ret = mmdc_do_write_level_calibration(sysinfo);
  471. if (ret) {
  472. printf("DDR3: Write level calibration error [%d]\n", ret);
  473. return ret;
  474. }
  475. ret = mmdc_do_dqs_calibration(sysinfo);
  476. if (ret) {
  477. printf("DDR3: DQS calibration error [%d]\n", ret);
  478. return ret;
  479. }
  480. #endif /* CONFIG_MX6_DDRCAL */
  481. return ret;
  482. }
  483. /* DRAM */
  484. static void dhcom_spl_dram_init(void)
  485. {
  486. enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
  487. if (is_mx6dq()) {
  488. mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
  489. &dhcom6dq_grp_ioregs);
  490. switch (ddr3_code) {
  491. default:
  492. printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
  493. printf(" choosing 1024 MB\n");
  494. /* fall through */
  495. case DH_DDR3_SIZE_1GIB:
  496. mx6_dram_cfg(&dhcom_ddr_64bit,
  497. &dhcom_mmdc_calib_4x2g_1066,
  498. &dhcom_mem_ddr_2g);
  499. break;
  500. case DH_DDR3_SIZE_2GIB:
  501. mx6_dram_cfg(&dhcom_ddr_64bit,
  502. &dhcom_mmdc_calib_4x4g_1066,
  503. &dhcom_mem_ddr_4g);
  504. break;
  505. }
  506. /* Perform DDR DRAM calibration */
  507. spl_dram_perform_cal(&dhcom_ddr_64bit);
  508. } else if (is_cpu_type(MXC_CPU_MX6DL)) {
  509. mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
  510. &dhcom6sdl_grp_ioregs);
  511. switch (ddr3_code) {
  512. default:
  513. printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
  514. printf(" choosing 1024 MB\n");
  515. /* fall through */
  516. case DH_DDR3_SIZE_1GIB:
  517. mx6_dram_cfg(&dhcom_ddr_64bit,
  518. &dhcom_mmdc_calib_4x2g_800,
  519. &dhcom_mem_ddr_2g);
  520. break;
  521. }
  522. /* Perform DDR DRAM calibration */
  523. spl_dram_perform_cal(&dhcom_ddr_64bit);
  524. } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
  525. mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
  526. &dhcom6sdl_grp_ioregs);
  527. switch (ddr3_code) {
  528. default:
  529. printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
  530. printf(" choosing 512 MB\n");
  531. /* fall through */
  532. case DH_DDR3_SIZE_512MIB:
  533. mx6_dram_cfg(&dhcom_ddr_32bit,
  534. &dhcom_mmdc_calib_2x2g_800,
  535. &dhcom_mem_ddr_2g);
  536. break;
  537. case DH_DDR3_SIZE_1GIB:
  538. mx6_dram_cfg(&dhcom_ddr_32bit,
  539. &dhcom_mmdc_calib_2x4g_800,
  540. &dhcom_mem_ddr_4g);
  541. break;
  542. }
  543. /* Perform DDR DRAM calibration */
  544. spl_dram_perform_cal(&dhcom_ddr_32bit);
  545. }
  546. }
  547. void board_init_f(ulong dummy)
  548. {
  549. /* setup AIPS and disable watchdog */
  550. arch_cpu_init();
  551. ccgr_init();
  552. gpr_init();
  553. /* setup GP timer */
  554. timer_init();
  555. setup_iomux_boardid();
  556. setup_iomux_ddrcode();
  557. setup_iomux_gpio();
  558. setup_iomux_enet();
  559. setup_iomux_sd();
  560. setup_iomux_spi();
  561. setup_iomux_uart();
  562. setup_iomux_usb();
  563. /* UART clocks enabled and gd valid - init serial console */
  564. preloader_console_init();
  565. /* DDR3 initialization */
  566. dhcom_spl_dram_init();
  567. /* Clear the BSS. */
  568. memset(__bss_start, 0, __bss_end - __bss_start);
  569. /* load/boot image from boot device */
  570. board_init_r(NULL, 0);
  571. }