kwbimage.cfg 4.8 KB

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  1. # SPDX-License-Identifier: GPL-2.0+
  2. #
  3. # Copyright (C) 2012
  4. # David Purdy <david.c.purdy@gmail.com>
  5. #
  6. # Based on Kirkwood support:
  7. # (C) Copyright 2009
  8. # Marvell Semiconductor <www.marvell.com>
  9. # Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
  10. # Refer doc/README.kwbimage for more details about how-to configure
  11. # and create kirkwood boot image
  12. #
  13. # Boot Media configurations
  14. BOOT_FROM nand
  15. NAND_ECC_MODE default
  16. NAND_PAGE_SIZE 0x0800
  17. # SOC registers configuration using bootrom header extension
  18. # Maximum KWBIMAGE_MAX_CONFIG configurations allowed
  19. # Configure RGMII-0 interface pad voltage to 1.8V
  20. DATA 0xffd100e0 0x1b1b1b9b
  21. #Dram initalization for SINGLE x16 CL=5 @ 400MHz
  22. DATA 0xffd01400 0x43000c30 # DDR Configuration register
  23. # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
  24. # bit23-14: zero
  25. # bit24: 1= enable exit self refresh mode on DDR access
  26. # bit25: 1 required
  27. # bit29-26: zero
  28. # bit31-30: 01
  29. DATA 0xffd01404 0x37543000 # DDR Controller Control Low
  30. # bit 4: 0=addr/cmd in smame cycle
  31. # bit 5: 0=clk is driven during self refresh, we don't care for APX
  32. # bit 6: 0=use recommended falling edge of clk for addr/cmd
  33. # bit14: 0=input buffer always powered up
  34. # bit18: 1=cpu lock transaction enabled
  35. # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
  36. # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
  37. # bit30-28: 3 required
  38. # bit31: 0=no additional STARTBURST delay
  39. DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
  40. # bit3-0: TRAS lsbs
  41. # bit7-4: TRCD
  42. # bit11- 8: TRP
  43. # bit15-12: TWR
  44. # bit19-16: TWTR
  45. # bit20: TRAS msb
  46. # bit23-21: 0x0
  47. # bit27-24: TRRD
  48. # bit31-28: TRTP
  49. DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
  50. # bit6-0: TRFC
  51. # bit8-7: TR2R
  52. # bit10-9: TR2W
  53. # bit12-11: TW2W
  54. # bit31-13: zero required
  55. DATA 0xffd01410 0x000000cc # DDR Address Control
  56. # bit1-0: 00, Cs0width=x8
  57. # bit3-2: 11, Cs0size=1Gb
  58. # bit5-4: 00, Cs1width=x8
  59. # bit7-6: 11, Cs1size=1Gb
  60. # bit9-8: 00, Cs2width=nonexistent
  61. # bit11-10: 00, Cs2size =nonexistent
  62. # bit13-12: 00, Cs3width=nonexistent
  63. # bit15-14: 00, Cs3size =nonexistent
  64. # bit16: 0, Cs0AddrSel
  65. # bit17: 0, Cs1AddrSel
  66. # bit18: 0, Cs2AddrSel
  67. # bit19: 0, Cs3AddrSel
  68. # bit31-20: 0 required
  69. DATA 0xffd01414 0x00000000 # DDR Open Pages Control
  70. # bit0: 0, OpenPage enabled
  71. # bit31-1: 0 required
  72. DATA 0xffd01418 0x00000000 # DDR Operation
  73. # bit3-0: 0x0, DDR cmd
  74. # bit31-4: 0 required
  75. DATA 0xffd0141c 0x00000c52 # DDR Mode
  76. # bit2-0: 2, BurstLen=2 required
  77. # bit3: 0, BurstType=0 required
  78. # bit6-4: 4, CL=5
  79. # bit7: 0, TestMode=0 normal
  80. # bit8: 0, DLL reset=0 normal
  81. # bit11-9: 6, auto-precharge write recovery ????????????
  82. # bit12: 0, PD must be zero
  83. # bit31-13: 0 required
  84. DATA 0xffd01420 0x00000040 # DDR Extended Mode
  85. # bit0: 0, DDR DLL enabled
  86. # bit1: 0, DDR drive strenght normal
  87. # bit2: 0, DDR ODT control lsd (disabled)
  88. # bit5-3: 000, required
  89. # bit6: 1, DDR ODT control msb, (disabled)
  90. # bit9-7: 000, required
  91. # bit10: 0, differential DQS enabled
  92. # bit11: 0, required
  93. # bit12: 0, DDR output buffer enabled
  94. # bit31-13: 0 required
  95. DATA 0xffd01424 0x0000f17f # DDR Controller Control High
  96. # bit2-0: 111, required
  97. # bit3 : 1 , MBUS Burst Chop disabled
  98. # bit6-4: 111, required
  99. # bit7 : 0
  100. # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
  101. # bit9 : 0 , no half clock cycle addition to dataout
  102. # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
  103. # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
  104. # bit15-12: 1111 required
  105. # bit31-16: 0 required
  106. DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
  107. DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
  108. DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
  109. DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
  110. # bit0: 1, Window enabled
  111. # bit1: 0, Write Protect disabled
  112. # bit3-2: 00, CS0 hit selected
  113. # bit23-4: ones, required
  114. # bit31-24: 0x0F, Size (i.e. 256MB)
  115. DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb
  116. DATA 0xffd0150c 0x00000000 # CS[2]n Size, window disabled
  117. DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
  118. DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
  119. DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
  120. # bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
  121. # bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
  122. # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
  123. # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
  124. DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
  125. # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
  126. # bit3-2: 01, ODT1 active NEVER!
  127. # bit31-4: zero, required
  128. DATA 0xffd0149c 0x0000e803 # CPU ODT Control
  129. DATA 0xffd01480 0x00000001 # DDR Initialization Control
  130. #bit0=1, enable DDR init upon this register write
  131. # End of Header extension
  132. DATA 0x0 0x0