usb_a9263.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2013
  4. * Stelian Pop <stelian.pop@leadtechdesign.com>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
  7. * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
  8. */
  9. #include <common.h>
  10. #include <init.h>
  11. #include <asm/arch/at91sam9_smc.h>
  12. #include <asm/arch/at91_common.h>
  13. #include <asm/arch/at91_matrix.h>
  14. #include <asm/arch/clk.h>
  15. #include <asm/arch/gpio.h>
  16. #include <asm-generic/gpio.h>
  17. #include <asm/global_data.h>
  18. #include <asm/io.h>
  19. #include <net.h>
  20. #include <netdev.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #ifdef CONFIG_CMD_NAND
  23. static void usb_a9263_nand_hw_init(void)
  24. {
  25. unsigned long csa;
  26. at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
  27. at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
  28. /* Enable CS3 */
  29. csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  30. writel(csa, &matrix->csa[0]);
  31. /* Configure SMC CS3 for NAND/SmartMedia */
  32. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  33. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  34. &smc->cs[3].setup);
  35. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  36. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  37. &smc->cs[3].pulse);
  38. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  39. &smc->cs[3].cycle);
  40. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  41. AT91_SMC_MODE_EXNW_DISABLE |
  42. AT91_SMC_MODE_DBW_8 |
  43. AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
  44. at91_periph_clk_enable(ATMEL_ID_PIOA);
  45. at91_periph_clk_enable(ATMEL_ID_PIOCDE);
  46. /* Configure RDY/BSY */
  47. gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
  48. gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  49. /* Enable NandFlash */
  50. gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
  51. gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  52. }
  53. #endif
  54. #ifdef CONFIG_MACB
  55. static void usb_a9263_macb_hw_init(void)
  56. {
  57. at91_periph_clk_enable(ATMEL_ID_EMAC);
  58. /*
  59. * Disable pull-up on:
  60. * RXDV (PC25) => PHY normal mode (not Test mode)
  61. * ERX0 (PE25) => PHY ADDR0
  62. * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
  63. *
  64. * PHY has internal weak pull-up/pull-down
  65. */
  66. gpio_request(GPIO_PIN_PC(25), "PHY mode");
  67. gpio_direction_input(GPIO_PIN_PC(25));
  68. gpio_request(GPIO_PIN_PE(25), "PHY ADDR0");
  69. gpio_direction_input(GPIO_PIN_PE(25));
  70. gpio_request(GPIO_PIN_PE(26), "PHY ADDR1");
  71. gpio_direction_input(GPIO_PIN_PE(26));
  72. at91_phy_reset();
  73. /* It will set proper pinmux for ports PC25, PE25-26 */
  74. at91_macb_hw_init();
  75. }
  76. #endif
  77. int board_init(void)
  78. {
  79. /* adress of boot parameters */
  80. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  81. #ifdef CONFIG_CMD_NAND
  82. usb_a9263_nand_hw_init();
  83. #endif
  84. #ifdef CONFIG_MACB
  85. usb_a9263_macb_hw_init();
  86. #endif
  87. #ifdef CONFIG_USB_OHCI_NEW
  88. at91_uhp_hw_init();
  89. #endif
  90. return 0;
  91. }
  92. int dram_init(void)
  93. {
  94. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  95. CONFIG_SYS_SDRAM_SIZE);
  96. return 0;
  97. }
  98. int board_eth_init(struct bd_info *bis)
  99. {
  100. int rc = 0;
  101. #ifdef CONFIG_MACB
  102. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001);
  103. #endif
  104. return rc;
  105. }