kwbimage-lsxhl.cfg 6.6 KB

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  1. # SPDX-License-Identifier: GPL-2.0+
  2. #
  3. # Copyright (c) 2012 Michael Walle
  4. # Michael Walle <michael@walle.cc>
  5. # Refer doc/README.kwbimage for more details about how-to configure
  6. # and create kirkwood boot image
  7. #
  8. # Boot Media configurations
  9. BOOT_FROM spi
  10. # SOC registers configuration using bootrom header extension
  11. # Maximum KWBIMAGE_MAX_CONFIG configurations allowed
  12. # Configure RGMII-0/1 interface pad voltage to 1.8V
  13. DATA 0xFFD100E0 0x1B1B9B9B
  14. # L2 RAM Timing 0
  15. DATA 0xFFD20134 0xBBBBBBBB
  16. # not further specified in HW manual, timing taken from original vendor port
  17. # L2 RAM Timing 1
  18. DATA 0xFFD20138 0x00BBBBBB
  19. # not further specified in HW manual, timing taken from original vendor port
  20. # DDR Configuration register
  21. DATA 0xFFD01400 0x43000618
  22. # bit13-0: 0x618, 1560 DDR2 clks refresh rate
  23. # bit23-14: 0 required
  24. # bit24: 1, enable exit self refresh mode on DDR access
  25. # bit25: 1 required
  26. # bit29-26: 0 required
  27. # bit31-30: 0b01 required
  28. # DDR Controller Control Low
  29. DATA 0xFFD01404 0x39543010
  30. # bit3-0: 0 required
  31. # bit4: 1, T2 mode, addr/cmd are driven for two cycles
  32. # bit5: 0, clk is driven during self refresh, we don't care for APX
  33. # bit6: 0, use recommended falling edge of clk for addr/cmd
  34. # bit11-7: 0 required
  35. # bit12: 1 required
  36. # bit13: 1 required
  37. # bit14: 0, input buffer always powered up
  38. # bit17-15: 0 required
  39. # bit18: 1, cpu lock transaction enabled
  40. # bit19: 0 required
  41. # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
  42. # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
  43. # bit30-28: 3 required
  44. # bit31: 0, no additional STARTBURST delay
  45. # DDR Timing (Low)
  46. DATA 0xFFD01408 0x22125441
  47. # bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
  48. # bit7-4: 4, 5 cycle tRCD
  49. # bit11-8: 4, 5 cyle tRP
  50. # bit15-12: 5, 6 cyle tWR
  51. # bit19-16: 2, 3 cyle tWTR
  52. # bit20: 1, 18 cycle tRAS (tRAS[4])
  53. # bit23-21: 0 required
  54. # bit27-24: 2, 3 cycle tRRD
  55. # bit31-28: 2, 3 cyle tRTP
  56. # DDR Timing (High)
  57. DATA 0xFFD0140C 0x00000832
  58. # bit6-0: 0x32, 50 cycle tRFC
  59. # bit8-7: 0, 1 cycle tR2R
  60. # bit10-9: 0, 1 cyle tR2W
  61. # bit12-11: 1, 2 cylce tW2W
  62. # bit31-13: 0 required
  63. # DDR Address Control
  64. DATA 0xFFD01410 0x0000000C
  65. # bit1-0: 0, Cs0width=x8
  66. # bit3-2: 3, Cs0size=1Gbit
  67. # bit5-4: 0, Cs1width=nonexistent
  68. # bit7-6: 0, Cs1size=nonexistent
  69. # bit9-8: 0, Cs2width=nonexistent
  70. # bit11-10: 0, Cs2size=nonexistent
  71. # bit13-12: 0, Cs3width=nonexistent
  72. # bit15-14: 0, Cs3size=nonexistent
  73. # bit16: 0, Cs0AddrSel
  74. # bit17: 0, Cs1AddrSel
  75. # bit18: 0, Cs2AddrSel
  76. # bit19: 0, Cs3AddrSel
  77. # bit31-20: 0 required
  78. # DDR Open Pages Control
  79. DATA 0xFFD01414 0x00000000
  80. # bit0: 0, OPEn=OpenPage enabled
  81. # bit31-1: 0 required
  82. # DDR Operation
  83. DATA 0xFFD01418 0x00000000
  84. # bit3-0: 0, Cmd=Normal SDRAM Mode
  85. # bit31-4: 0 required
  86. # DDR Mode
  87. DATA 0xFFD0141C 0x00000652
  88. # bit2-0: 2, Burst Length (2 required)
  89. # bit3: 0, Burst Type (0 required)
  90. # bit6-4: 5, CAS Latency (CL) 5
  91. # bit7: 0, (Test Mode) Normal operation
  92. # bit8: 0, (Reset DLL) Normal operation
  93. # bit11-9: 3, Write recovery for auto-precharge (3 required)
  94. # bit12: 0, Fast Active power down exit time (0 required)
  95. # bit31-13: 0 required
  96. # DDR Extended Mode
  97. DATA 0xFFD01420 0x00000006
  98. # bit0: 0, DRAM DLL enabled
  99. # bit1: 1, DRAM drive strength reduced
  100. # bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination)
  101. # bit5-3: 0 required
  102. # bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination)
  103. # bit9-7: 0 required
  104. # bit10: 0, differential DQS enabled
  105. # bit11: 0 required
  106. # bit12: 0, DRAM output buffer enabled
  107. # bit31-13: 0 required
  108. # DDR Controller Control High
  109. DATA 0xFFD01424 0x0000F17F
  110. # bit2-0: 0x7 required
  111. # bit3: 1, MBUS Burst Chop disabled
  112. # bit6-4: 0x7 required
  113. # bit7: 0 required (???)
  114. # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
  115. # bit9: 0, no half clock cycle addition to dataout
  116. # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
  117. # bit11: 0, 1/4 clock cycle skew disabled for write mesh
  118. # bit15-12: 0xf required
  119. # bit31-16: 0 required
  120. # DDR2 ODT Read Timing (default values)
  121. DATA 0xFFD01428 0x00085520
  122. # bit3-0: 0 required
  123. # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
  124. # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
  125. # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
  126. # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
  127. # bit31-20: 0 required
  128. # DDR2 ODT Write Timing (default values)
  129. DATA 0xFFD0147C 0x00008552
  130. # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
  131. # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
  132. # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
  133. # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
  134. # bit31-16: 0 required
  135. # CS[0]n Base address
  136. DATA 0xFFD01500 0x00000000
  137. # at 0x0
  138. # CS[0]n Size
  139. DATA 0xFFD01504 0x0FFFFFF1
  140. # bit0: 1, Window enabled
  141. # bit1: 0, Write Protect disabled
  142. # bit3-2: 0x0, CS0 hit selected
  143. # bit23-4: 0xfffff required
  144. # bit31-24: 0x0f, Size (i.e. 256MB)
  145. # CS[1]n Size
  146. DATA 0xFFD0150C 0x00000000
  147. # window disabled
  148. # CS[2]n Size
  149. DATA 0xFFD01514 0x00000000
  150. # window disabled
  151. # CS[3]n Size
  152. DATA 0xFFD0151C 0x00000000
  153. # window disabled
  154. # DDR ODT Control (Low)
  155. DATA 0xFFD01494 0x00010000
  156. # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
  157. # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
  158. # bit15-8: 0 required
  159. # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
  160. # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
  161. # bit31-24: 0 required
  162. # DDR ODT Control (High)
  163. DATA 0xFFD01498 0x00000000
  164. # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
  165. # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
  166. # bit31-4 0 required
  167. # CPU ODT Control
  168. DATA 0xFFD0149C 0x0000E80F
  169. # bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
  170. # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
  171. # bit9-8: 0, Internal ODT assertion is controlled by fiels
  172. # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
  173. # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
  174. # bit14: 1, M_STARTBURST_IN ODT enabled
  175. # bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
  176. # bit20-16: 0, Pad N channel driving strength for ODT
  177. # bit25-21: 0, Pad P channel driving strength for ODT
  178. # bit31-26: 0 required
  179. # DDR Initialization Control
  180. DATA 0xFFD01480 0x00000001
  181. # bit0: 1, enable DDR init upon this register write
  182. # bit31-1: 0, required
  183. # End of Header extension
  184. DATA 0x0 0x0