at91sam9n12ek.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Atmel Corporation
  4. * Josh Wu <josh.wu@atmel.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <vsprintf.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/at91sam9x5_matrix.h>
  13. #include <asm/arch/at91sam9_smc.h>
  14. #include <asm/arch/at91_common.h>
  15. #include <asm/arch/at91_rstc.h>
  16. #include <asm/arch/at91_pio.h>
  17. #include <asm/arch/clk.h>
  18. #include <debug_uart.h>
  19. #include <lcd.h>
  20. #include <atmel_hlcdc.h>
  21. #include <netdev.h>
  22. #ifdef CONFIG_LCD_INFO
  23. #include <nand.h>
  24. #include <version.h>
  25. #endif
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /* ------------------------------------------------------------------------- */
  28. /*
  29. * Miscelaneous platform dependent initialisations
  30. */
  31. #ifdef CONFIG_NAND_ATMEL
  32. static void at91sam9n12ek_nand_hw_init(void)
  33. {
  34. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  35. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  36. unsigned long csa;
  37. /* Assign CS3 to NAND/SmartMedia Interface */
  38. csa = readl(&matrix->ebicsa);
  39. csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  40. /* Configure databus */
  41. csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
  42. /* Configure IO drive */
  43. csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  44. writel(csa, &matrix->ebicsa);
  45. /* Configure SMC CS3 for NAND/SmartMedia */
  46. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  47. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  48. &smc->cs[3].setup);
  49. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  50. AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  51. &smc->cs[3].pulse);
  52. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
  53. &smc->cs[3].cycle);
  54. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  55. AT91_SMC_MODE_EXNW_DISABLE |
  56. #ifdef CONFIG_SYS_NAND_DBW_16
  57. AT91_SMC_MODE_DBW_16 |
  58. #else /* CONFIG_SYS_NAND_DBW_8 */
  59. AT91_SMC_MODE_DBW_8 |
  60. #endif
  61. AT91_SMC_MODE_TDF_CYCLE(1),
  62. &smc->cs[3].mode);
  63. /* Configure RDY/BSY pin */
  64. at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
  65. /* Configure ENABLE pin for NandFlash */
  66. at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
  67. at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
  68. at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
  69. at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
  70. at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
  71. }
  72. #endif
  73. #ifdef CONFIG_LCD
  74. vidinfo_t panel_info = {
  75. .vl_col = 480,
  76. .vl_row = 272,
  77. .vl_clk = 9000000,
  78. .vl_bpix = LCD_BPP,
  79. .vl_sync = 0,
  80. .vl_tft = 1,
  81. .vl_hsync_len = 5,
  82. .vl_left_margin = 8,
  83. .vl_right_margin = 43,
  84. .vl_vsync_len = 10,
  85. .vl_upper_margin = 4,
  86. .vl_lower_margin = 12,
  87. .mmio = ATMEL_BASE_LCDC,
  88. };
  89. void lcd_enable(void)
  90. {
  91. at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */
  92. }
  93. void lcd_disable(void)
  94. {
  95. at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */
  96. }
  97. #ifdef CONFIG_LCD_INFO
  98. void lcd_show_board_info(void)
  99. {
  100. ulong dram_size, nand_size;
  101. int i;
  102. char temp[32];
  103. lcd_printf("%s\n", U_BOOT_VERSION);
  104. lcd_printf("ATMEL Corp\n");
  105. lcd_printf("at91@atmel.com\n");
  106. lcd_printf("%s CPU at %s MHz\n",
  107. ATMEL_CPU_NAME,
  108. strmhz(temp, get_cpu_clk_rate()));
  109. dram_size = 0;
  110. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  111. dram_size += gd->bd->bi_dram[i].size;
  112. nand_size = 0;
  113. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  114. nand_size += get_nand_dev_by_index(i)->size;
  115. lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
  116. dram_size >> 20,
  117. nand_size >> 20);
  118. }
  119. #endif /* CONFIG_LCD_INFO */
  120. #endif /* CONFIG_LCD */
  121. #ifdef CONFIG_KS8851_MLL
  122. void at91sam9n12ek_ks8851_hw_init(void)
  123. {
  124. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  125. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  126. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  127. &smc->cs[2].setup);
  128. writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
  129. AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
  130. &smc->cs[2].pulse);
  131. writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
  132. &smc->cs[2].cycle);
  133. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  134. AT91_SMC_MODE_EXNW_DISABLE |
  135. AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
  136. AT91_SMC_MODE_TDF_CYCLE(1),
  137. &smc->cs[2].mode);
  138. /* Configure NCS2 PIN */
  139. at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
  140. }
  141. #endif
  142. #ifdef CONFIG_USB_ATMEL
  143. void at91sam9n12ek_usb_hw_init(void)
  144. {
  145. at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
  146. }
  147. #endif
  148. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  149. void board_debug_uart_init(void)
  150. {
  151. at91_seriald_hw_init();
  152. }
  153. #endif
  154. #ifdef CONFIG_BOARD_EARLY_INIT_F
  155. int board_early_init_f(void)
  156. {
  157. #ifdef CONFIG_DEBUG_UART
  158. debug_uart_init();
  159. #endif
  160. return 0;
  161. }
  162. #endif
  163. int board_init(void)
  164. {
  165. /* adress of boot parameters */
  166. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  167. #ifdef CONFIG_NAND_ATMEL
  168. at91sam9n12ek_nand_hw_init();
  169. #endif
  170. #ifdef CONFIG_LCD
  171. at91_lcd_hw_init();
  172. #endif
  173. #ifdef CONFIG_KS8851_MLL
  174. at91sam9n12ek_ks8851_hw_init();
  175. #endif
  176. #ifdef CONFIG_USB_ATMEL
  177. at91sam9n12ek_usb_hw_init();
  178. #endif
  179. return 0;
  180. }
  181. #ifdef CONFIG_KS8851_MLL
  182. int board_eth_init(struct bd_info *bis)
  183. {
  184. return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
  185. }
  186. #endif
  187. int dram_init(void)
  188. {
  189. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  190. CONFIG_SYS_SDRAM_SIZE);
  191. return 0;
  192. }
  193. #if defined(CONFIG_SPL_BUILD)
  194. #include <spl.h>
  195. #include <nand.h>
  196. void at91_spl_board_init(void)
  197. {
  198. #ifdef CONFIG_SD_BOOT
  199. at91_mci_hw_init();
  200. #elif CONFIG_NAND_BOOT
  201. at91sam9n12ek_nand_hw_init();
  202. #elif CONFIG_SPI_BOOT
  203. at91_spi0_hw_init(1 << 4);
  204. #endif
  205. }
  206. #include <asm/arch/atmel_mpddrc.h>
  207. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  208. {
  209. ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  210. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  211. ATMEL_MPDDRC_CR_NR_ROW_13 |
  212. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  213. ATMEL_MPDDRC_CR_NB_8BANKS |
  214. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
  215. ddr2->rtr = 0x411;
  216. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  217. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  218. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  219. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  220. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  221. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  222. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  223. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  224. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  225. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  226. 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  227. 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  228. ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  229. 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  230. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  231. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  232. }
  233. void mem_init(void)
  234. {
  235. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  236. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  237. struct atmel_mpddrc_config ddr2;
  238. unsigned long csa;
  239. ddr2_conf(&ddr2);
  240. /* enable DDR2 clock */
  241. writel(AT91_PMC_DDR, &pmc->scer);
  242. /* Chip select 1 is for DDR2/SDRAM */
  243. csa = readl(&matrix->ebicsa);
  244. csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
  245. csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
  246. csa |= AT91_MATRIX_EBI_DBPD_OFF;
  247. csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  248. writel(csa, &matrix->ebicsa);
  249. /* DDRAM2 Controller initialize */
  250. ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
  251. }
  252. #endif