nas220.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
  4. *
  5. * Based on sheevaplug.c originally written by
  6. * Prafulla Wadaskar <prafulla@marvell.com>
  7. * (C) Copyright 2009
  8. * Marvell Semiconductor <www.marvell.com>
  9. */
  10. #include <common.h>
  11. #include <init.h>
  12. #include <miiphy.h>
  13. #include <net.h>
  14. #include <asm/global_data.h>
  15. #include <asm/mach-types.h>
  16. #include <asm/arch/soc.h>
  17. #include <asm/arch/mpp.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/io.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. int board_early_init_f(void)
  22. {
  23. /*
  24. * default gpio configuration
  25. */
  26. mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH,
  27. NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH);
  28. /* Multi-Purpose Pins Functionality configuration */
  29. static const u32 kwmpp_config[] = {
  30. MPP0_NF_IO2,
  31. MPP1_NF_IO3,
  32. MPP2_NF_IO4,
  33. MPP3_NF_IO5,
  34. MPP4_NF_IO6,
  35. MPP5_NF_IO7,
  36. MPP6_SYSRST_OUTn,
  37. MPP7_SPI_SCn,
  38. MPP8_TW_SDA,
  39. MPP9_TW_SCK,
  40. MPP10_UART0_TXD,
  41. MPP11_UART0_RXD,
  42. MPP12_GPO,
  43. MPP13_GPIO,
  44. MPP14_GPIO,
  45. MPP15_SATA0_ACTn,
  46. MPP16_SATA1_ACTn,
  47. MPP17_SATA0_PRESENTn,
  48. MPP18_NF_IO0,
  49. MPP19_NF_IO1,
  50. MPP20_GPIO,
  51. MPP21_GPIO,
  52. MPP22_GPIO,
  53. MPP23_GPIO,
  54. MPP24_GPIO,
  55. MPP25_GPIO,
  56. MPP26_GPIO,
  57. MPP27_GPIO,
  58. MPP28_GPIO,
  59. MPP29_GPIO,
  60. MPP30_GPIO,
  61. MPP31_GPIO,
  62. MPP32_GPIO,
  63. MPP33_GPIO,
  64. MPP34_GPIO,
  65. MPP35_GPIO,
  66. 0
  67. };
  68. kirkwood_mpp_conf(kwmpp_config, NULL);
  69. return 0;
  70. }
  71. int board_init(void)
  72. {
  73. /*
  74. * arch number of board
  75. */
  76. gd->bd->bi_arch_number = MACH_TYPE_RD88F6192_NAS;
  77. /* adress of boot parameters */
  78. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  79. return 0;
  80. }
  81. #ifdef CONFIG_RESET_PHY_R
  82. /* Configure and enable MV88E1116 PHY */
  83. void reset_phy(void)
  84. {
  85. u16 reg;
  86. u16 devadr;
  87. char *name = "egiga0";
  88. if (miiphy_set_current_dev(name))
  89. return;
  90. /* command to read PHY dev address */
  91. if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
  92. printf("Err..%s could not read PHY dev address\n", __func__);
  93. return;
  94. }
  95. /*
  96. * Enable RGMII delay on Tx and Rx for CPU port
  97. * Ref: sec 4.7.2 of chip datasheet
  98. */
  99. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
  100. miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
  101. reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
  102. miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
  103. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
  104. /* reset the phy */
  105. miiphy_reset(name, devadr);
  106. printf("88E1116 Initialized on %s\n", name);
  107. }
  108. #endif /* CONFIG_RESET_PHY_R */