goflexhome.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2021
  4. * Tony Dinh <mibodhi@gmail.com>
  5. * Suriyan Ramasami <suriyan.r@gmail.com>
  6. *
  7. * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
  8. *
  9. * Based on dockstar.c originally written by
  10. * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
  11. *
  12. * Based on sheevaplug.c originally written by
  13. * Prafulla Wadaskar <prafulla@marvell.com>
  14. * (C) Copyright 2009
  15. * Marvell Semiconductor <www.marvell.com>
  16. */
  17. #include <common.h>
  18. #include <bootstage.h>
  19. #include <init.h>
  20. #include <miiphy.h>
  21. #include <net.h>
  22. #include <asm/global_data.h>
  23. #include <asm/mach-types.h>
  24. #include <asm/arch/soc.h>
  25. #include <asm/arch/mpp.h>
  26. #include <asm/arch/cpu.h>
  27. #include <asm/io.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. int board_early_init_f(void)
  30. {
  31. /* Multi-Purpose Pins Functionality configuration */
  32. static const u32 kwmpp_config[] = {
  33. MPP0_NF_IO2,
  34. MPP1_NF_IO3,
  35. MPP2_NF_IO4,
  36. MPP3_NF_IO5,
  37. MPP4_NF_IO6,
  38. MPP5_NF_IO7,
  39. MPP6_SYSRST_OUTn,
  40. MPP7_GPO,
  41. MPP8_UART0_RTS,
  42. MPP9_UART0_CTS,
  43. MPP10_UART0_TXD,
  44. MPP11_UART0_RXD,
  45. MPP12_SD_CLK,
  46. MPP13_SD_CMD,
  47. MPP14_SD_D0,
  48. MPP15_SD_D1,
  49. MPP16_SD_D2,
  50. MPP17_SD_D3,
  51. MPP18_NF_IO0,
  52. MPP19_NF_IO1,
  53. MPP20_GPIO,
  54. MPP21_GPIO,
  55. MPP22_GPIO,
  56. MPP23_GPIO,
  57. MPP24_GPIO,
  58. MPP25_GPIO,
  59. MPP26_GPIO,
  60. MPP27_GPIO,
  61. MPP28_GPIO,
  62. MPP29_TSMP9,
  63. MPP30_GPIO,
  64. MPP31_GPIO,
  65. MPP32_GPIO,
  66. MPP33_GPIO,
  67. MPP34_GPIO,
  68. MPP35_GPIO,
  69. MPP36_GPIO,
  70. MPP37_GPIO,
  71. MPP38_GPIO,
  72. MPP39_GPIO,
  73. MPP40_GPIO,
  74. MPP41_GPIO,
  75. MPP42_GPIO,
  76. MPP43_GPIO,
  77. MPP44_GPIO,
  78. MPP45_GPIO,
  79. MPP46_GPIO,
  80. MPP47_GPIO,
  81. MPP48_GPIO,
  82. MPP49_GPIO,
  83. 0
  84. };
  85. /*
  86. * default gpio configuration
  87. * There are maximum 64 gpios controlled through 2 sets of registers
  88. * the below configuration configures mainly initial LED status
  89. */
  90. mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW,
  91. GOFLEXHOME_OE_VAL_HIGH,
  92. GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
  93. kirkwood_mpp_conf(kwmpp_config, NULL);
  94. return 0;
  95. }
  96. int board_init(void)
  97. {
  98. /*
  99. * arch number of board
  100. */
  101. gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
  102. /* address of boot parameters */
  103. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  104. return 0;
  105. }
  106. static int fdt_get_phy_addr(const char *path)
  107. {
  108. const void *fdt = gd->fdt_blob;
  109. const u32 *reg;
  110. const u32 *val;
  111. int node, phandle, addr;
  112. /* Find the node by its full path */
  113. node = fdt_path_offset(fdt, path);
  114. if (node >= 0) {
  115. /* Look up phy-handle */
  116. val = fdt_getprop(fdt, node, "phy-handle", NULL);
  117. if (val) {
  118. phandle = fdt32_to_cpu(*val);
  119. if (!phandle)
  120. return -1;
  121. /* Follow it to its node */
  122. node = fdt_node_offset_by_phandle(fdt, phandle);
  123. if (node) {
  124. /* Look up reg */
  125. reg = fdt_getprop(fdt, node, "reg", NULL);
  126. if (reg) {
  127. addr = fdt32_to_cpu(*reg);
  128. return addr;
  129. }
  130. }
  131. }
  132. }
  133. return -1;
  134. }
  135. #ifdef CONFIG_RESET_PHY_R
  136. /* Configure and enable MV88E1116 PHY */
  137. void reset_phy(void)
  138. {
  139. u16 reg;
  140. int phyaddr;
  141. char *name = "ethernet-controller@72000";
  142. char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
  143. if (miiphy_set_current_dev(name))
  144. return;
  145. phyaddr = fdt_get_phy_addr(eth0_path);
  146. if (phyaddr < 0)
  147. return;
  148. /*
  149. * Enable RGMII delay on Tx and Rx for CPU port
  150. * Ref: sec 4.7.2 of chip datasheet
  151. */
  152. miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
  153. miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
  154. reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
  155. miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
  156. miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
  157. /* reset the phy */
  158. miiphy_reset(name, phyaddr);
  159. printf("88E1116 Initialized on %s\n", name);
  160. }
  161. #endif /* CONFIG_RESET_PHY_R */
  162. #if CONFIG_IS_ENABLED(BOOTSTAGE)
  163. #define GREEN_LED (1 << 14)
  164. #define ORANGE_LED (1 << 15)
  165. #define BOTH_LEDS (GREEN_LED | ORANGE_LED)
  166. #define NEITHER_LED 0
  167. static void set_leds(u32 leds, u32 blinking)
  168. {
  169. struct kwgpio_registers *r;
  170. u32 oe;
  171. u32 bl;
  172. r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
  173. oe = readl(&r->oe) | BOTH_LEDS;
  174. writel(oe & ~leds, &r->oe); /* active low */
  175. bl = readl(&r->blink_en) & ~BOTH_LEDS;
  176. writel(bl | blinking, &r->blink_en);
  177. }
  178. void show_boot_progress(int val)
  179. {
  180. switch (val) {
  181. case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
  182. set_leds(BOTH_LEDS, NEITHER_LED);
  183. break;
  184. case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
  185. set_leds(GREEN_LED, GREEN_LED);
  186. break;
  187. default:
  188. if (val < 0) /* error */
  189. set_leds(ORANGE_LED, ORANGE_LED);
  190. break;
  191. }
  192. }
  193. #endif