openrd.c 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Net Insight <www.netinsight.net>
  5. * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
  6. *
  7. * Based on sheevaplug.c:
  8. * (C) Copyright 2009
  9. * Marvell Semiconductor <www.marvell.com>
  10. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  11. */
  12. #include <common.h>
  13. #include <init.h>
  14. #include <miiphy.h>
  15. #include <net.h>
  16. #include <asm/global_data.h>
  17. #include <asm/mach-types.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/soc.h>
  20. #include <asm/arch/mpp.h>
  21. #include "openrd.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. int board_early_init_f(void)
  24. {
  25. /*
  26. * default gpio configuration
  27. * There are maximum 64 gpios controlled through 2 sets of registers
  28. * the below configuration configures mainly initial LED status
  29. */
  30. mvebu_config_gpio(OPENRD_OE_VAL_LOW,
  31. OPENRD_OE_VAL_HIGH,
  32. OPENRD_OE_LOW, OPENRD_OE_HIGH);
  33. /* Multi-Purpose Pins Functionality configuration */
  34. static const u32 kwmpp_config[] = {
  35. MPP0_NF_IO2,
  36. MPP1_NF_IO3,
  37. MPP2_NF_IO4,
  38. MPP3_NF_IO5,
  39. MPP4_NF_IO6,
  40. MPP5_NF_IO7,
  41. MPP6_SYSRST_OUTn,
  42. MPP7_GPO,
  43. MPP8_TW_SDA,
  44. MPP9_TW_SCK,
  45. MPP10_UART0_TXD,
  46. MPP11_UART0_RXD,
  47. MPP12_SD_CLK,
  48. MPP13_SD_CMD, /* Alt UART1_TXD */
  49. MPP14_SD_D0, /* Alt UART1_RXD */
  50. MPP15_SD_D1,
  51. MPP16_SD_D2,
  52. MPP17_SD_D3,
  53. MPP18_NF_IO0,
  54. MPP19_NF_IO1,
  55. MPP20_GE1_0,
  56. MPP21_GE1_1,
  57. MPP22_GE1_2,
  58. MPP23_GE1_3,
  59. MPP24_GE1_4,
  60. MPP25_GE1_5,
  61. MPP26_GE1_6,
  62. MPP27_GE1_7,
  63. MPP28_GPIO,
  64. MPP29_TSMP9,
  65. MPP30_GE1_10,
  66. MPP31_GE1_11,
  67. MPP32_GE1_12,
  68. MPP33_GE1_13,
  69. MPP34_GPIO, /* UART1 / SD sel */
  70. MPP35_TDM_CH0_TX_QL,
  71. MPP36_TDM_SPI_CS1,
  72. MPP37_TDM_CH2_TX_QL,
  73. MPP38_TDM_CH2_RX_QL,
  74. MPP39_AUDIO_I2SBCLK,
  75. MPP40_AUDIO_I2SDO,
  76. MPP41_AUDIO_I2SLRC,
  77. MPP42_AUDIO_I2SMCLK,
  78. MPP43_AUDIO_I2SDI,
  79. MPP44_AUDIO_EXTCLK,
  80. MPP45_TDM_PCLK,
  81. MPP46_TDM_FS,
  82. MPP47_TDM_DRX,
  83. MPP48_TDM_DTX,
  84. MPP49_TDM_CH0_RX_QL,
  85. 0
  86. };
  87. kirkwood_mpp_conf(kwmpp_config, NULL);
  88. return 0;
  89. }
  90. int board_init(void)
  91. {
  92. /*
  93. * arch number of board
  94. */
  95. #if defined(CONFIG_BOARD_IS_OPENRD_BASE)
  96. gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
  97. #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
  98. gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
  99. #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
  100. gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
  101. #endif
  102. /* adress of boot parameters */
  103. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  104. return 0;
  105. }
  106. #ifdef CONFIG_RESET_PHY_R
  107. /* Configure and enable MV88E1116/88E1121 PHY */
  108. void mv_phy_init(char *name)
  109. {
  110. u16 reg;
  111. u16 devadr;
  112. if (miiphy_set_current_dev(name))
  113. return;
  114. /* command to read PHY dev address */
  115. if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
  116. printf("Err..%s could not read PHY dev address\n", __func__);
  117. return;
  118. }
  119. /*
  120. * Enable RGMII delay on Tx and Rx for CPU port
  121. * Ref: sec 4.7.2 of chip datasheet
  122. */
  123. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
  124. miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
  125. reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
  126. miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
  127. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
  128. /* reset the phy */
  129. miiphy_reset(name, devadr);
  130. printf(PHY_NO" Initialized on %s\n", name);
  131. }
  132. void reset_phy(void)
  133. {
  134. mv_phy_init("egiga0");
  135. #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
  136. /* Kirkwood ethernet driver is written with the assumption that in case
  137. * of multiple PHYs, their addresses are consecutive. But unfortunately
  138. * in case of OpenRD-Client, PHY addresses are not consecutive.*/
  139. miiphy_write("egiga1", 0xEE, 0xEE, 24);
  140. #endif
  141. #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
  142. defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
  143. /* configure and initialize both PHY's */
  144. mv_phy_init("egiga1");
  145. #endif
  146. }
  147. #endif /* CONFIG_RESET_PHY_R */