board.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <dm/device-internal.h>
  8. #include <env.h>
  9. #include <env_internal.h>
  10. #include <i2c.h>
  11. #include <init.h>
  12. #include <mmc.h>
  13. #include <phy.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/soc.h>
  18. #include <linux/delay.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /* IO expander I2C device */
  21. #define I2C_IO_EXP_ADDR 0x22
  22. #define I2C_IO_CFG_REG_0 0x6
  23. #define I2C_IO_DATA_OUT_REG_0 0x2
  24. #define I2C_IO_REG_0_SATA_OFF 2
  25. #define I2C_IO_REG_0_USB_H_OFF 1
  26. /* The pin control values are the same for DB and Espressobin */
  27. #define PINCTRL_NB_REG_VALUE 0x000173fa
  28. #define PINCTRL_SB_REG_VALUE 0x00007a23
  29. /* Ethernet switch registers */
  30. /* SMI addresses for multi-chip mode */
  31. #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
  32. #define MVEBU_SW_G2_SMI_ADDR (28)
  33. /* Multi-chip mode */
  34. #define MVEBU_SW_SMI_DATA_REG (1)
  35. #define MVEBU_SW_SMI_CMD_REG (0)
  36. #define SW_SMI_CMD_REG_ADDR_OFF 0
  37. #define SW_SMI_CMD_DEV_ADDR_OFF 5
  38. #define SW_SMI_CMD_SMI_OP_OFF 10
  39. #define SW_SMI_CMD_SMI_MODE_OFF 12
  40. #define SW_SMI_CMD_SMI_BUSY_OFF 15
  41. /* Single-chip mode */
  42. /* Switch Port Registers */
  43. #define MVEBU_SW_LINK_CTRL_REG (1)
  44. #define MVEBU_SW_PORT_CTRL_REG (4)
  45. #define MVEBU_SW_PORT_BASE_VLAN (6)
  46. /* Global 2 Registers */
  47. #define MVEBU_G2_SMI_PHY_CMD_REG (24)
  48. #define MVEBU_G2_SMI_PHY_DATA_REG (25)
  49. /*
  50. * Memory Controller Registers
  51. *
  52. * Assembled based on public information:
  53. * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
  54. * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
  55. *
  56. * And checked against the written register values for the various topologies:
  57. * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
  58. */
  59. #define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4)
  60. #define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf
  61. #define A3700_MC_CTRL2_SDRAM_TYPE_OFFS 4
  62. #define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
  63. #define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
  64. int board_early_init_f(void)
  65. {
  66. return 0;
  67. }
  68. int board_init(void)
  69. {
  70. /* adress of boot parameters */
  71. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  72. return 0;
  73. }
  74. #ifdef CONFIG_BOARD_LATE_INIT
  75. int board_late_init(void)
  76. {
  77. char *ptr = (char *)&default_environment[0];
  78. struct udevice *dev;
  79. struct mmc *mmc_dev;
  80. bool ddr4, emmc;
  81. const char *mac;
  82. char eth[10];
  83. int i;
  84. if (!of_machine_is_compatible("globalscale,espressobin"))
  85. return 0;
  86. /* Find free buffer in default_environment[] for new variables */
  87. while (*ptr != '\0' && *(ptr+1) != '\0') ptr++;
  88. ptr += 2;
  89. /*
  90. * Ensure that 'env default -a' does not erase permanent MAC addresses
  91. * stored in env variables: $ethaddr, $eth1addr, $eth2addr and $eth3addr
  92. */
  93. mac = env_get("ethaddr");
  94. if (mac && strlen(mac) <= 17)
  95. ptr += sprintf(ptr, "ethaddr=%s", mac) + 1;
  96. for (i = 1; i <= 3; i++) {
  97. sprintf(eth, "eth%daddr", i);
  98. mac = env_get(eth);
  99. if (mac && strlen(mac) <= 17)
  100. ptr += sprintf(ptr, "%s=%s", eth, mac) + 1;
  101. }
  102. /* If the memory controller has been configured for DDR4, we're running on v7 */
  103. ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
  104. & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
  105. /* eMMC is mmc dev num 1 */
  106. mmc_dev = find_mmc_device(1);
  107. emmc = (mmc_dev && mmc_get_op_cond(mmc_dev, true) == 0);
  108. /* if eMMC is not present then remove it from DM */
  109. if (!emmc && mmc_dev) {
  110. dev = mmc_dev->dev;
  111. device_remove(dev, DM_REMOVE_NORMAL);
  112. device_unbind(dev);
  113. }
  114. /* Ensure that 'env default -a' set correct value to $fdtfile */
  115. if (ddr4 && emmc)
  116. strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7-emmc.dtb");
  117. else if (ddr4)
  118. strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7.dtb");
  119. else if (emmc)
  120. strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-emmc.dtb");
  121. else
  122. strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin.dtb");
  123. return 0;
  124. }
  125. #endif
  126. /* Board specific AHCI / SATA enable code */
  127. int board_ahci_enable(void)
  128. {
  129. struct udevice *dev;
  130. int ret;
  131. u8 buf[8];
  132. /* Only DB requres this configuration */
  133. if (!of_machine_is_compatible("marvell,armada-3720-db"))
  134. return 0;
  135. /* Configure IO exander PCA9555: 7bit address 0x22 */
  136. ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
  137. if (ret) {
  138. printf("Cannot find PCA9555: %d\n", ret);
  139. return 0;
  140. }
  141. ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
  142. if (ret) {
  143. printf("Failed to read IO expander value via I2C\n");
  144. return -EIO;
  145. }
  146. /*
  147. * Enable SATA power via IO expander connected via I2C by setting
  148. * the corresponding bit to output mode to enable power for SATA
  149. */
  150. buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
  151. ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
  152. if (ret) {
  153. printf("Failed to set IO expander via I2C\n");
  154. return -EIO;
  155. }
  156. return 0;
  157. }
  158. /* Board specific xHCI enable code */
  159. int board_xhci_enable(fdt_addr_t base)
  160. {
  161. struct udevice *dev;
  162. int ret;
  163. u8 buf[8];
  164. /* Only DB requres this configuration */
  165. if (!of_machine_is_compatible("marvell,armada-3720-db"))
  166. return 0;
  167. /* Configure IO exander PCA9555: 7bit address 0x22 */
  168. ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
  169. if (ret) {
  170. printf("Cannot find PCA9555: %d\n", ret);
  171. return 0;
  172. }
  173. printf("Enable USB VBUS\n");
  174. /*
  175. * Read configuration (direction) and set VBUS pin as output
  176. * (reset pin = output)
  177. */
  178. ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
  179. if (ret) {
  180. printf("Failed to read IO expander value via I2C\n");
  181. return -EIO;
  182. }
  183. buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
  184. ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
  185. if (ret) {
  186. printf("Failed to set IO expander via I2C\n");
  187. return -EIO;
  188. }
  189. /* Read VBUS output value and disable it */
  190. ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  191. if (ret) {
  192. printf("Failed to read IO expander value via I2C\n");
  193. return -EIO;
  194. }
  195. buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
  196. ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  197. if (ret) {
  198. printf("Failed to set IO expander via I2C\n");
  199. return -EIO;
  200. }
  201. /*
  202. * Required delay for configuration to settle - must wait for
  203. * power on port is disabled in case VBUS signal was high,
  204. * required 3 seconds delay to let VBUS signal fully settle down
  205. */
  206. mdelay(3000);
  207. /* Enable VBUS power: Set output value of VBUS pin as enabled */
  208. buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
  209. ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  210. if (ret) {
  211. printf("Failed to set IO expander via I2C\n");
  212. return -EIO;
  213. }
  214. mdelay(500); /* required delay to let output value settle */
  215. return 0;
  216. }
  217. /* Helper function for accessing switch devices in multi-chip connection mode */
  218. static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
  219. int smi_addr, int reg, u16 value)
  220. {
  221. u16 smi_cmd = 0;
  222. if (bus->write(bus, dev_smi_addr, 0,
  223. MVEBU_SW_SMI_DATA_REG, value) != 0) {
  224. printf("Error writing to the PHY addr=%02x reg=%02x\n",
  225. smi_addr, reg);
  226. return -EFAULT;
  227. }
  228. smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
  229. (1 << SW_SMI_CMD_SMI_MODE_OFF) |
  230. (1 << SW_SMI_CMD_SMI_OP_OFF) |
  231. (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
  232. (reg << SW_SMI_CMD_REG_ADDR_OFF);
  233. if (bus->write(bus, dev_smi_addr, 0,
  234. MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
  235. printf("Error writing to the PHY addr=%02x reg=%02x\n",
  236. smi_addr, reg);
  237. return -EFAULT;
  238. }
  239. return 0;
  240. }
  241. /* Bring-up board-specific network stuff */
  242. int board_network_enable(struct mii_dev *bus)
  243. {
  244. if (!of_machine_is_compatible("globalscale,espressobin"))
  245. return 0;
  246. /*
  247. * FIXME: remove this code once Topaz driver gets available
  248. * A3720 Community Board Only
  249. * Configure Topaz switch (88E6341)
  250. * Restrict output to ports 1,2,3 only from port 0 (CPU)
  251. * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
  252. */
  253. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
  254. MVEBU_SW_PORT_BASE_VLAN, BIT(0));
  255. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
  256. MVEBU_SW_PORT_BASE_VLAN, BIT(0));
  257. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
  258. MVEBU_SW_PORT_BASE_VLAN, BIT(0));
  259. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
  260. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  261. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
  262. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  263. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
  264. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  265. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
  266. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  267. /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
  268. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
  269. MVEBU_SW_LINK_CTRL_REG, 0xe002);
  270. /* Power up PHY 1, 2, 3 (through Global 2 registers) */
  271. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  272. MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
  273. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  274. MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
  275. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  276. MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
  277. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  278. MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
  279. return 0;
  280. }
  281. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  282. int ft_board_setup(void *blob, struct bd_info *bd)
  283. {
  284. int ret;
  285. int spi_off;
  286. int parts_off;
  287. int part_off;
  288. /* Fill SPI MTD partitions for Linux kernel on Espressobin */
  289. if (!of_machine_is_compatible("globalscale,espressobin"))
  290. return 0;
  291. spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
  292. if (spi_off < 0)
  293. return 0;
  294. /* Do not touch partitions if they are already defined */
  295. if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
  296. return 0;
  297. parts_off = fdt_add_subnode(blob, spi_off, "partitions");
  298. if (parts_off < 0) {
  299. printf("Can't add partitions node: %s\n", fdt_strerror(parts_off));
  300. return 0;
  301. }
  302. ret = fdt_setprop_string(blob, parts_off, "compatible", "fixed-partitions");
  303. if (ret < 0) {
  304. printf("Can't set compatible property: %s\n", fdt_strerror(ret));
  305. return 0;
  306. }
  307. ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
  308. if (ret < 0) {
  309. printf("Can't set #address-cells property: %s\n", fdt_strerror(ret));
  310. return 0;
  311. }
  312. ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
  313. if (ret < 0) {
  314. printf("Can't set #size-cells property: %s\n", fdt_strerror(ret));
  315. return 0;
  316. }
  317. /* Add u-boot-env partition */
  318. part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
  319. if (part_off < 0) {
  320. printf("Can't add partition@u-boot-env node: %s\n", fdt_strerror(part_off));
  321. return 0;
  322. }
  323. ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
  324. if (ret < 0) {
  325. printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
  326. return 0;
  327. }
  328. ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
  329. if (ret < 0) {
  330. printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
  331. return 0;
  332. }
  333. ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
  334. if (ret < 0) {
  335. printf("Can't set partition@u-boot-env label property: %s\n", fdt_strerror(ret));
  336. return 0;
  337. }
  338. /* Add firmware partition */
  339. part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
  340. if (part_off < 0) {
  341. printf("Can't add partition@firmware node: %s\n", fdt_strerror(part_off));
  342. return 0;
  343. }
  344. ret = fdt_setprop_u32(blob, part_off, "reg", 0);
  345. if (ret < 0) {
  346. printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
  347. return 0;
  348. }
  349. ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
  350. if (ret < 0) {
  351. printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
  352. return 0;
  353. }
  354. ret = fdt_setprop_string(blob, part_off, "label", "firmware");
  355. if (ret < 0) {
  356. printf("Can't set partition@firmware label property: %s\n", fdt_strerror(ret));
  357. return 0;
  358. }
  359. return 0;
  360. }
  361. #endif