mux.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * mux.c
  4. *
  5. * Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1)
  6. *
  7. * Copyright (C) 2017 Hannes Schmelzer <hannes.schmelzer@br-automation.com>
  8. * B&R Industrial Automation GmbH - http://www.br-automation.com
  9. *
  10. */
  11. #include <common.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/mux.h>
  15. #include <asm/io.h>
  16. #include <i2c.h>
  17. static struct module_pin_mux spi0_pin_mux[] = {
  18. /* SPI0_SCLK */
  19. {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
  20. /* SPI0_D0 */
  21. {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
  22. /* SPI0_D1 */
  23. {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
  24. /* SPI0_CS0 */
  25. {OFFSET(spi0_cs0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
  26. /* SPI0_CS1 */
  27. {OFFSET(spi0_cs1), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
  28. {-1},
  29. };
  30. static struct module_pin_mux spi1_pin_mux[] = {
  31. /* SPI1_SCLK */
  32. {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
  33. /* SPI1_D0 */
  34. {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
  35. /* SPI1_D1 */
  36. {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
  37. /* SPI1_CS0 */
  38. {OFFSET(mcasp0_ahclkr), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
  39. /* SPI1_CS1 */
  40. {OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
  41. {-1},
  42. };
  43. static struct module_pin_mux dcan0_pin_mux[] = {
  44. /* DCAN0 TX */
  45. {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
  46. /* DCAN0 RX */
  47. {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
  48. {-1},
  49. };
  50. static struct module_pin_mux dcan1_pin_mux[] = {
  51. /* DCAN1 TX */
  52. {OFFSET(uart0_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
  53. /* DCAN1 RX */
  54. {OFFSET(uart0_rtsn), MODE(2) | RXACTIVE},
  55. {-1},
  56. };
  57. static struct module_pin_mux gpios[] = {
  58. /* GPIO0_7 - LVDS_EN */
  59. {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
  60. /* GPIO0_20 - BKLT_PWM (timer7) */
  61. {OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)},
  62. /* GPIO2_4 - DISON */
  63. {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
  64. /* GPIO1_24 - RGB_EN */
  65. {OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
  66. /* GPIO1_28 - nPD */
  67. {OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)},
  68. /* GPIO2_5 - Watchdog */
  69. {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
  70. /* GPIO2_0 - ResetOut */
  71. {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},
  72. /* GPIO2_2 - BKLT_EN */
  73. {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
  74. /* GPIO1_17 - GPIO0 */
  75. {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
  76. /* GPIO1_18 - GPIO1 */
  77. {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)},
  78. /* GPIO1_19 - GPIO2 */
  79. {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)},
  80. /* GPIO1_22 - GPIO3 */
  81. {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)},
  82. /* GPIO1_23 - GPIO4 */
  83. {OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS | RXACTIVE)},
  84. /* GPIO1_25 - GPIO5 */
  85. {OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS | RXACTIVE)},
  86. /* GPIO3_7 - GPIO6 */
  87. {OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)},
  88. /* GPIO3_8 - GPIO7 */
  89. {OFFSET(emu1), (MODE(7) | PULLUDDIS | RXACTIVE)},
  90. /* GPIO3_18 - GPIO8 */
  91. {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
  92. /* GPIO3_19 - GPIO9 */
  93. {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDDIS | RXACTIVE)},
  94. /* GPIO3_20 - GPIO10 */
  95. {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
  96. /* GPIO3_21 - GPIO11 */
  97. {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS | RXACTIVE)},
  98. /* GPIO2_28 - DRAM-strapping */
  99. {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN)},
  100. /* GPIO2_4 - not routed (Pin U6) */
  101. {OFFSET(gpmc_wen), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  102. /* GPIO2_5 - not routed (Pin T6) */
  103. {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  104. /* GPIO2_28 - not routed (Pin G15) */
  105. {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  106. /* GPIO3_18 - not routed (Pin B12) */
  107. {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  108. {-1},
  109. };
  110. static struct module_pin_mux uart0_pin_mux[] = {
  111. /* UART0_RXD */
  112. {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  113. /* UART0_TXD */
  114. {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
  115. {-1},
  116. };
  117. static struct module_pin_mux uart234_pin_mux[] = {
  118. /* UART2_RXD */
  119. {OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  120. /* UART2_TXD */
  121. {OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},
  122. /* UART3_RXD */
  123. {OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  124. /* UART3_TXD */
  125. {OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)},
  126. /* UART3_RTS */
  127. {OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)},
  128. /* UART3_CTS */
  129. {OFFSET(mmc0_clk), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  130. /* UART4_RXD */
  131. {OFFSET(mii1_txd3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  132. /* UART4_TXD */
  133. {OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)},
  134. /* UART4_RTS */
  135. {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN)},
  136. /* UART4_CTS */
  137. {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  138. {-1},
  139. };
  140. static struct module_pin_mux i2c_pin_mux[] = {
  141. /* I2C0_DATA */
  142. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  143. /* I2C0_SCLK */
  144. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  145. /* I2C1_DATA */
  146. {OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  147. /* I2C1_SCLK */
  148. {OFFSET(uart1_txd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  149. {-1},
  150. };
  151. static struct module_pin_mux eth_pin_mux[] = {
  152. /* ETH1 */
  153. {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* ETH1_REFCLK */
  154. {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRSDV */
  155. {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXER */
  156. {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
  157. {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
  158. {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
  159. {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
  160. {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
  161. /* ETH2 */
  162. {OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* ETH2_REFCLK */
  163. {OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRSDV */
  164. {OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXER */
  165. {OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
  166. {OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */
  167. {OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */
  168. {OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
  169. {OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
  170. /* gpio2_19, gpio 3_4, not connected on board */
  171. {OFFSET(mii1_rxd2), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
  172. {OFFSET(mii1_rxdv), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
  173. /* ETH Management */
  174. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
  175. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  176. {-1},
  177. };
  178. static struct module_pin_mux mmc1_pin_mux[] = {
  179. {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
  180. {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
  181. {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
  182. {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
  183. {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
  184. {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
  185. {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
  186. {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
  187. {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
  188. {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
  189. {-1},
  190. };
  191. static struct module_pin_mux lcd_pin_mux[] = {
  192. {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
  193. {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
  194. {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
  195. {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
  196. {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
  197. {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
  198. {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
  199. {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
  200. {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
  201. {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
  202. {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
  203. {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
  204. {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
  205. {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
  206. {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
  207. {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
  208. {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
  209. {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
  210. {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
  211. {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
  212. {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
  213. {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
  214. {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
  215. {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
  216. {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
  217. {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
  218. {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
  219. {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
  220. {-1},
  221. };
  222. void enable_uart0_pin_mux(void)
  223. {
  224. configure_module_pin_mux(uart0_pin_mux);
  225. }
  226. void enable_i2c_pin_mux(void)
  227. {
  228. configure_module_pin_mux(i2c_pin_mux);
  229. }
  230. void enable_board_pin_mux(void)
  231. {
  232. configure_module_pin_mux(eth_pin_mux);
  233. configure_module_pin_mux(spi0_pin_mux);
  234. configure_module_pin_mux(spi1_pin_mux);
  235. configure_module_pin_mux(dcan0_pin_mux);
  236. configure_module_pin_mux(dcan1_pin_mux);
  237. configure_module_pin_mux(uart234_pin_mux);
  238. configure_module_pin_mux(mmc1_pin_mux);
  239. configure_module_pin_mux(lcd_pin_mux);
  240. configure_module_pin_mux(gpios);
  241. }