ag101p.dts 1.5 KB

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  1. /dts-v1/;
  2. / {
  3. compatible = "nds32 ag101p";
  4. #address-cells = <1>;
  5. #size-cells = <1>;
  6. interrupt-parent = <&intc>;
  7. aliases {
  8. uart0 = &serial0;
  9. ethernet0 = &mac0;
  10. } ;
  11. chosen {
  12. /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */
  13. bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7";
  14. stdout-path = "uart0:38400n8";
  15. tick-timer = &timer0;
  16. };
  17. memory@0 {
  18. device_type = "memory";
  19. reg = <0x00000000 0x40000000>;
  20. };
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. cpu@0 {
  25. compatible = "andestech,n13";
  26. reg = <0>;
  27. /* FIXME: to fill correct frqeuency */
  28. clock-frequency = <60000000>;
  29. };
  30. };
  31. intc: interrupt-controller {
  32. compatible = "andestech,atnointc010";
  33. #interrupt-cells = <1>;
  34. interrupt-controller;
  35. };
  36. serial0: serial@99600000 {
  37. compatible = "andestech,uart16550", "ns16550a";
  38. reg = <0x99600000 0x1000>;
  39. interrupts = <7 4>;
  40. clock-frequency = <14745600>;
  41. reg-shift = <2>;
  42. no-loopback-test = <1>;
  43. };
  44. timer0: timer@98400000 {
  45. compatible = "andestech,attmr010";
  46. reg = <0x98400000 0x1000>;
  47. interrupts = <19 4>;
  48. clock-frequency = <15000000>;
  49. };
  50. mac0: mac@90900000 {
  51. compatible = "andestech,atmac100";
  52. reg = <0x90900000 0x1000>;
  53. interrupts = <25 4>;
  54. };
  55. mmc0: mmc@98e00000 {
  56. compatible = "andestech,atfsdc010";
  57. max-frequency = <30000000>;
  58. fifo-depth = <0x10>;
  59. reg = <0x98e00000 0x1000>;
  60. interrupts = <5 4>;
  61. cap-sd-highspeed;
  62. };
  63. };