ae3xx.dts 2.1 KB

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  1. /dts-v1/;
  2. / {
  3. compatible = "nds32 ae3xx";
  4. #address-cells = <1>;
  5. #size-cells = <1>;
  6. interrupt-parent = <&intc>;
  7. aliases {
  8. uart0 = &serial0;
  9. ethernet0 = &mac0;
  10. spi0 = &spi;
  11. } ;
  12. chosen {
  13. /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */
  14. bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
  15. stdout-path = "uart0:38400n8";
  16. tick-timer = &timer0;
  17. };
  18. memory@0 {
  19. device_type = "memory";
  20. reg = <0x00000000 0x40000000>;
  21. };
  22. spiclk: virt_100mhz {
  23. #clock-cells = <0>;
  24. compatible = "fixed-clock";
  25. clock-frequency = <100000000>;
  26. };
  27. cpus {
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. cpu@0 {
  31. compatible = "andestech,n13";
  32. reg = <0>;
  33. /* FIXME: to fill correct frqeuency */
  34. clock-frequency = <60000000>;
  35. };
  36. };
  37. intc: interrupt-controller {
  38. compatible = "andestech,atnointc010";
  39. #interrupt-cells = <1>;
  40. interrupt-controller;
  41. };
  42. serial0: serial@f0300000 {
  43. compatible = "andestech,uart16550", "ns16550a";
  44. reg = <0xf0300000 0x1000>;
  45. interrupts = <7 4>;
  46. clock-frequency = <14745600>;
  47. reg-shift = <2>;
  48. reg-offset = <32>;
  49. no-loopback-test = <1>;
  50. };
  51. timer0: timer@f0400000 {
  52. compatible = "andestech,atcpit100";
  53. reg = <0xf0400000 0x1000>;
  54. interrupts = <2 4>;
  55. clock-frequency = <30000000>;
  56. };
  57. mac0: mac@e0100000 {
  58. compatible = "andestech,atmac100";
  59. reg = <0xe0100000 0x1000>;
  60. interrupts = <25 4>;
  61. };
  62. mmc0: mmc@f0e00000 {
  63. compatible = "andestech,atfsdc010";
  64. max-frequency = <100000000>;
  65. fifo-depth = <0x10>;
  66. reg = <0xf0e00000 0x1000>;
  67. interrupts = <17 4>;
  68. };
  69. nor@0,0 {
  70. compatible = "cfi-flash";
  71. reg = <0x88000000 0x1000>;
  72. bank-width = <2>;
  73. device-width = <1>;
  74. };
  75. spi: spi@f0b00000 {
  76. compatible = "andestech,atcspi200";
  77. reg = <0xf0b00000 0x1000>;
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. num-cs = <1>;
  81. clocks = <&spiclk>;
  82. interrupts = <3 4>;
  83. flash@0 {
  84. compatible = "jedec,spi-nor";
  85. spi-max-frequency = <50000000>;
  86. reg = <0>;
  87. spi-cpol;
  88. spi-cpha;
  89. };
  90. };
  91. };