sg-regs.h 3.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * UniPhier SG (SoC Glue) block registers
  4. *
  5. * Copyright (C) 2011-2015 Copyright (C) 2011-2015 Panasonic Corporation
  6. * Copyright (C) 2016-2017 Socionext Inc.
  7. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  8. */
  9. #ifndef UNIPHIER_SG_REGS_H
  10. #define UNIPHIER_SG_REGS_H
  11. #include <linux/bitops.h>
  12. #ifndef __ASSEMBLY__
  13. #include <linux/compiler.h>
  14. #ifdef CONFIG_ARCH_UNIPHIER_V8_MULTI
  15. extern void __iomem *sg_base;
  16. #else
  17. #define sg_base ((void __iomem *)SG_BASE)
  18. #endif
  19. #endif /* __ASSEMBLY__ */
  20. /* Base Address */
  21. #define SG_BASE 0x5f800000
  22. /* Revision */
  23. #define SG_REVISION 0x0000
  24. #define SG_REVISION_TYPE_MASK GENMASK(23, 16)
  25. #define SG_REVISION_MODEL_MASK GENMASK(10, 8)
  26. #define SG_REVISION_REV_MASK GENMASK(4, 0)
  27. /* Memory Configuration */
  28. #define SG_MEMCONF 0x0400
  29. #define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
  30. #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
  31. #define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
  32. #define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
  33. #define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
  34. #define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
  35. #define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
  36. #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
  37. #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
  38. #define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
  39. #define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
  40. #define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
  41. #define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
  42. #define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
  43. #define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
  44. #define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
  45. #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
  46. #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
  47. #define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
  48. #define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
  49. #define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
  50. #define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
  51. #define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
  52. #define SG_MEMCONF_CH2_SZ_1G ((0x1 << 26) | (0x01 << 16))
  53. #define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
  54. #define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
  55. #define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
  56. /* PH1-LD6b, ProXstream2, PH1-LD20 only */
  57. #define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
  58. #define SG_MEMCONF_SPARSEMEM (0x1 << 4)
  59. #define SG_USBPHYCTRL 0x0500
  60. #define SG_ETPHYPSHUT 0x0554
  61. #define SG_ETPHYCNT 0x0550
  62. /* Pin Control */
  63. #define SG_PINCTRL_BASE 0x1000
  64. /* PH1-Pro4, PH1-Pro5 */
  65. #define SG_LOADPINCTRL 0x1700
  66. /* Input Enable */
  67. #define SG_IECTRL 0x1d00
  68. /* Pin Monitor */
  69. #define SG_PINMON0 0x00100100
  70. #define SG_PINMON2 0x00100108
  71. #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
  72. #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
  73. #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
  74. #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
  75. #define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
  76. #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
  77. #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
  78. #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
  79. #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
  80. #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
  81. #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
  82. #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
  83. #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
  84. #endif /* UNIPHIER_SG_REGS_H */