board2.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010,2011
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <env.h>
  9. #include <errno.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <ns16550.h>
  13. #include <usb.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <asm/arch-tegra/ap.h>
  17. #include <asm/arch-tegra/board.h>
  18. #include <asm/arch-tegra/cboot.h>
  19. #include <asm/arch-tegra/clk_rst.h>
  20. #include <asm/arch-tegra/pmc.h>
  21. #include <asm/arch-tegra/pmu.h>
  22. #include <asm/arch-tegra/sys_proto.h>
  23. #include <asm/arch-tegra/uart.h>
  24. #include <asm/arch-tegra/warmboot.h>
  25. #include <asm/arch-tegra/gpu.h>
  26. #include <asm/arch-tegra/usb.h>
  27. #include <asm/arch-tegra/xusb-padctl.h>
  28. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  29. #include <asm/arch/clock.h>
  30. #endif
  31. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  32. #include <asm/arch/funcmux.h>
  33. #include <asm/arch/pinmux.h>
  34. #endif
  35. #include <asm/arch/tegra.h>
  36. #ifdef CONFIG_TEGRA_CLOCK_SCALING
  37. #include <asm/arch/emc.h>
  38. #endif
  39. #include "emc.h"
  40. DECLARE_GLOBAL_DATA_PTR;
  41. #ifdef CONFIG_SPL_BUILD
  42. /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
  43. U_BOOT_DRVINFO(tegra_gpios) = {
  44. "gpio_tegra"
  45. };
  46. #endif
  47. __weak void pinmux_init(void) {}
  48. __weak void pin_mux_usb(void) {}
  49. __weak void pin_mux_spi(void) {}
  50. __weak void pin_mux_mmc(void) {}
  51. __weak void gpio_early_init_uart(void) {}
  52. __weak void pin_mux_display(void) {}
  53. __weak void start_cpu_fan(void) {}
  54. __weak void cboot_late_init(void) {}
  55. #if defined(CONFIG_TEGRA_NAND)
  56. __weak void pin_mux_nand(void)
  57. {
  58. funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
  59. }
  60. #endif
  61. /*
  62. * Routine: power_det_init
  63. * Description: turn off power detects
  64. */
  65. static void power_det_init(void)
  66. {
  67. #if defined(CONFIG_TEGRA20)
  68. struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  69. /* turn off power detects */
  70. writel(0, &pmc->pmc_pwr_det_latch);
  71. writel(0, &pmc->pmc_pwr_det);
  72. #endif
  73. }
  74. __weak int tegra_board_id(void)
  75. {
  76. return -1;
  77. }
  78. #ifdef CONFIG_DISPLAY_BOARDINFO
  79. int checkboard(void)
  80. {
  81. int board_id = tegra_board_id();
  82. printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
  83. if (board_id != -1)
  84. printf(", ID: %d\n", board_id);
  85. printf("\n");
  86. return 0;
  87. }
  88. #endif /* CONFIG_DISPLAY_BOARDINFO */
  89. __weak int tegra_lcd_pmic_init(int board_it)
  90. {
  91. return 0;
  92. }
  93. __weak int nvidia_board_init(void)
  94. {
  95. return 0;
  96. }
  97. /*
  98. * Routine: board_init
  99. * Description: Early hardware init.
  100. */
  101. int board_init(void)
  102. {
  103. __maybe_unused int err;
  104. __maybe_unused int board_id;
  105. /* Do clocks and UART first so that printf() works */
  106. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  107. clock_init();
  108. clock_verify();
  109. #endif
  110. tegra_gpu_config();
  111. #ifdef CONFIG_TEGRA_SPI
  112. pin_mux_spi();
  113. #endif
  114. #ifdef CONFIG_MMC_SDHCI_TEGRA
  115. pin_mux_mmc();
  116. #endif
  117. /* Init is handled automatically in the driver-model case */
  118. #if defined(CONFIG_DM_VIDEO)
  119. pin_mux_display();
  120. #endif
  121. /* boot param addr */
  122. gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
  123. power_det_init();
  124. #ifdef CONFIG_SYS_I2C_TEGRA
  125. # ifdef CONFIG_TEGRA_PMU
  126. if (pmu_set_nominal())
  127. debug("Failed to select nominal voltages\n");
  128. # ifdef CONFIG_TEGRA_CLOCK_SCALING
  129. err = board_emc_init();
  130. if (err)
  131. debug("Memory controller init failed: %d\n", err);
  132. # endif
  133. # endif /* CONFIG_TEGRA_PMU */
  134. #endif /* CONFIG_SYS_I2C_TEGRA */
  135. #ifdef CONFIG_USB_EHCI_TEGRA
  136. pin_mux_usb();
  137. #endif
  138. #if defined(CONFIG_DM_VIDEO)
  139. board_id = tegra_board_id();
  140. err = tegra_lcd_pmic_init(board_id);
  141. if (err) {
  142. debug("Failed to set up LCD PMIC\n");
  143. return err;
  144. }
  145. #endif
  146. #ifdef CONFIG_TEGRA_NAND
  147. pin_mux_nand();
  148. #endif
  149. tegra_xusb_padctl_init();
  150. #ifdef CONFIG_TEGRA_LP0
  151. /* save Sdram params to PMC 2, 4, and 24 for WB0 */
  152. warmboot_save_sdram_params();
  153. /* prepare the WB code to LP0 location */
  154. warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
  155. #endif
  156. return nvidia_board_init();
  157. }
  158. void board_cleanup_before_linux(void)
  159. {
  160. /* power down UPHY PLL */
  161. tegra_xusb_padctl_exit();
  162. }
  163. #ifdef CONFIG_BOARD_EARLY_INIT_F
  164. static void __gpio_early_init(void)
  165. {
  166. }
  167. void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
  168. int board_early_init_f(void)
  169. {
  170. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  171. if (!clock_early_init_done())
  172. clock_early_init();
  173. #endif
  174. #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
  175. #define USBCMD_FS2 (1 << 15)
  176. {
  177. struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
  178. writel(USBCMD_FS2, &usbctlr->usb_cmd);
  179. }
  180. #endif
  181. /* Do any special system timer/TSC setup */
  182. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  183. # if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  184. if (!tegra_cpu_is_non_secure())
  185. # endif
  186. arch_timer_init();
  187. #endif
  188. #if defined(CONFIG_DISABLE_SDMMC1_EARLY)
  189. /*
  190. * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
  191. * We do this because earlier bootloaders have enabled power to
  192. * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
  193. * results in power being back-driven into the SD-card and SDMMC1
  194. * HW, which is 'bad' as per the HW team.
  195. *
  196. * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
  197. * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
  198. * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
  199. * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
  200. * voltage turns off. Since the SDCard voltage is no longer there, the
  201. * SDMMC CLK/DAT lines are backdriving into what essentially is a
  202. * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
  203. *
  204. * Note that this can probably be removed when we change over to storing
  205. * all BL components on QSPI on Nano, and U-Boot then becomes the first
  206. * one to turn on SDMMC1 power. Another fix would be to have CBoot
  207. * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
  208. */
  209. reset_set_enable(PERIPH_ID_SDMMC1, 1);
  210. clock_set_enable(PERIPH_ID_SDMMC1, 0);
  211. #endif /* CONFIG_DISABLE_SDMMC1_EARLY */
  212. pinmux_init();
  213. board_init_uart_f();
  214. /* Initialize periph GPIOs */
  215. gpio_early_init();
  216. gpio_early_init_uart();
  217. return 0;
  218. }
  219. #endif /* EARLY_INIT */
  220. int board_late_init(void)
  221. {
  222. #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  223. if (tegra_cpu_is_non_secure()) {
  224. printf("CPU is in NS mode\n");
  225. env_set("cpu_ns_mode", "1");
  226. } else {
  227. env_set("cpu_ns_mode", "");
  228. }
  229. #endif
  230. start_cpu_fan();
  231. cboot_late_init();
  232. return 0;
  233. }
  234. /*
  235. * In some SW environments, a memory carve-out exists to house a secure
  236. * monitor, a trusted OS, and/or various statically allocated media buffers.
  237. *
  238. * This carveout exists at the highest possible address that is within a
  239. * 32-bit physical address space.
  240. *
  241. * This function returns the total size of this carve-out. At present, the
  242. * returned value is hard-coded for simplicity. In the future, it may be
  243. * possible to determine the carve-out size:
  244. * - By querying some run-time information source, such as:
  245. * - A structure passed to U-Boot by earlier boot software.
  246. * - SoC registers.
  247. * - A call into the secure monitor.
  248. * - In the per-board U-Boot configuration header, based on knowledge of the
  249. * SW environment that U-Boot is being built for.
  250. *
  251. * For now, we support two configurations in U-Boot:
  252. * - 32-bit ports without any form of carve-out.
  253. * - 64 bit ports which are assumed to use a carve-out of a conservatively
  254. * hard-coded size.
  255. */
  256. static ulong carveout_size(void)
  257. {
  258. #ifdef CONFIG_ARM64
  259. return SZ_512M;
  260. #elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
  261. // BASE+SIZE might not == 4GB. If so, we want the carveout to cover
  262. // from BASE to 4GB, not BASE to BASE+SIZE.
  263. return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1);
  264. #else
  265. return 0;
  266. #endif
  267. }
  268. /*
  269. * Determine the amount of usable RAM below 4GiB, taking into account any
  270. * carve-out that may be assigned.
  271. */
  272. static ulong usable_ram_size_below_4g(void)
  273. {
  274. ulong total_size_below_4g;
  275. ulong usable_size_below_4g;
  276. /*
  277. * The total size of RAM below 4GiB is the lesser address of:
  278. * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
  279. * (b) The size RAM physically present in the system.
  280. */
  281. if (gd->ram_size < SZ_2G)
  282. total_size_below_4g = gd->ram_size;
  283. else
  284. total_size_below_4g = SZ_2G;
  285. /* Calculate usable RAM by subtracting out any carve-out size */
  286. usable_size_below_4g = total_size_below_4g - carveout_size();
  287. return usable_size_below_4g;
  288. }
  289. /*
  290. * Represent all available RAM in either one or two banks.
  291. *
  292. * The first bank describes any usable RAM below 4GiB.
  293. * The second bank describes any RAM above 4GiB.
  294. *
  295. * This split is driven by the following requirements:
  296. * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
  297. * property for memory below and above the 4GiB boundary. The layout of that
  298. * DT property is directly driven by the entries in the U-Boot bank array.
  299. * - The potential existence of a carve-out at the end of RAM below 4GiB can
  300. * only be represented using multiple banks.
  301. *
  302. * Explicitly removing the carve-out RAM from the bank entries makes the RAM
  303. * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
  304. * command-line.
  305. *
  306. * This does mean that the DT U-Boot passes to the Linux kernel will not
  307. * include this RAM in /memory/reg at all. An alternative would be to include
  308. * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
  309. * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
  310. * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
  311. * mapping, so either way is acceptable.
  312. *
  313. * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
  314. * start address of that bank cannot be represented in the 32-bit .size
  315. * field.
  316. */
  317. int dram_init_banksize(void)
  318. {
  319. int err;
  320. /* try to compute DRAM bank size based on cboot DTB first */
  321. err = cboot_dram_init_banksize();
  322. if (err == 0)
  323. return err;
  324. /* fall back to default DRAM bank size computation */
  325. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  326. gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
  327. #ifdef CONFIG_PCI
  328. gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
  329. #endif
  330. #ifdef CONFIG_PHYS_64BIT
  331. if (gd->ram_size > SZ_2G) {
  332. gd->bd->bi_dram[1].start = 0x100000000;
  333. gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
  334. } else
  335. #endif
  336. {
  337. gd->bd->bi_dram[1].start = 0;
  338. gd->bd->bi_dram[1].size = 0;
  339. }
  340. return 0;
  341. }
  342. /*
  343. * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
  344. * 32-bits of the physical address space. Cap the maximum usable RAM area
  345. * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
  346. * boundary that most devices can address. Also, don't let U-Boot use any
  347. * carve-out, as mentioned above.
  348. *
  349. * This function is called before dram_init_banksize(), so we can't simply
  350. * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
  351. */
  352. ulong board_get_usable_ram_top(ulong total_size)
  353. {
  354. ulong ram_top;
  355. /* try to get top of usable RAM based on cboot DTB first */
  356. ram_top = cboot_get_usable_ram_top(total_size);
  357. if (ram_top > 0)
  358. return ram_top;
  359. /* fall back to default usable RAM computation */
  360. return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
  361. }