board.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <ns16550.h>
  12. #include <spl.h>
  13. #include <asm/cache.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  17. #include <asm/arch/clock.h>
  18. #endif
  19. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  20. #include <asm/arch/funcmux.h>
  21. #endif
  22. #if IS_ENABLED(CONFIG_TEGRA_MC)
  23. #include <asm/arch/mc.h>
  24. #endif
  25. #include <asm/arch/tegra.h>
  26. #include <asm/arch-tegra/ap.h>
  27. #include <asm/arch-tegra/board.h>
  28. #include <asm/arch-tegra/cboot.h>
  29. #include <asm/arch-tegra/pmc.h>
  30. #include <asm/arch-tegra/sys_proto.h>
  31. #include <asm/arch-tegra/warmboot.h>
  32. void save_boot_params_ret(void);
  33. DECLARE_GLOBAL_DATA_PTR;
  34. enum {
  35. /* UARTs which we can enable */
  36. UARTA = 1 << 0,
  37. UARTB = 1 << 1,
  38. UARTC = 1 << 2,
  39. UARTD = 1 << 3,
  40. UARTE = 1 << 4,
  41. UART_COUNT = 5,
  42. };
  43. static bool from_spl __section(".data");
  44. #ifndef CONFIG_SPL_BUILD
  45. void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
  46. unsigned long r3)
  47. {
  48. from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
  49. /*
  50. * The logic for this is somewhat indirect. The purpose of the marker
  51. * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
  52. * was loaded from a read-only instance of itself, which is something
  53. * that can happen in secure boot setups. So basically the presence
  54. * of the marker is an indication that U-Boot was loaded by one such
  55. * special variant of U-Boot. Conversely, the absence of the marker
  56. * indicates that this instance of U-Boot was loaded by something
  57. * other than a special U-Boot. This could be SPL, but it could just
  58. * as well be one of any number of other first stage bootloaders.
  59. */
  60. if (from_spl)
  61. cboot_save_boot_params(r0, r1, r2, r3);
  62. save_boot_params_ret();
  63. }
  64. #endif
  65. bool spl_was_boot_source(void)
  66. {
  67. return from_spl;
  68. }
  69. #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  70. #if !defined(CONFIG_TEGRA124)
  71. #error tegra_cpu_is_non_secure has only been validated on Tegra124
  72. #endif
  73. bool tegra_cpu_is_non_secure(void)
  74. {
  75. /*
  76. * This register reads 0xffffffff in non-secure mode. This register
  77. * only implements bits 31:20, so the lower bits will always read 0 in
  78. * secure mode. Thus, the lower bits are an indicator for secure vs.
  79. * non-secure mode.
  80. */
  81. struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  82. uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
  83. return (mc_s_cfg0 & 1) == 1;
  84. }
  85. #endif
  86. #if IS_ENABLED(CONFIG_TEGRA_MC)
  87. /* Read the RAM size directly from the memory controller */
  88. static phys_size_t query_sdram_size(void)
  89. {
  90. struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  91. u32 emem_cfg;
  92. phys_size_t size_bytes;
  93. emem_cfg = readl(&mc->mc_emem_cfg);
  94. #if defined(CONFIG_TEGRA20)
  95. debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
  96. size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
  97. #else
  98. debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
  99. #ifndef CONFIG_PHYS_64BIT
  100. /*
  101. * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
  102. * and will wrap. Clip the reported size to the maximum that a 32-bit
  103. * variable can represent (rounded to a page).
  104. */
  105. if (emem_cfg >= 4096) {
  106. size_bytes = U32_MAX & ~(0x1000 - 1);
  107. } else
  108. #endif
  109. {
  110. /* RAM size EMC is programmed to. */
  111. size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
  112. #ifndef CONFIG_ARM64
  113. /*
  114. * If all RAM fits within 32-bits, it can be accessed without
  115. * LPAE, so go test the RAM size. Otherwise, we can't access
  116. * all the RAM, and get_ram_size() would get confused, so
  117. * avoid using it. There's no reason we should need this
  118. * validation step anyway.
  119. */
  120. if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
  121. size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
  122. size_bytes);
  123. #endif
  124. }
  125. #endif
  126. #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
  127. /* External memory limited to 2047 MB due to IROM/HI-VEC */
  128. if (size_bytes == SZ_2G)
  129. size_bytes -= SZ_1M;
  130. #endif
  131. return size_bytes;
  132. }
  133. #endif
  134. int dram_init(void)
  135. {
  136. int err;
  137. /* try to initialize DRAM from cboot DTB first */
  138. err = cboot_dram_init();
  139. if (err == 0)
  140. return 0;
  141. #if IS_ENABLED(CONFIG_TEGRA_MC)
  142. /* We do not initialise DRAM here. We just query the size */
  143. gd->ram_size = query_sdram_size();
  144. #endif
  145. return 0;
  146. }
  147. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  148. static int uart_configs[] = {
  149. #if defined(CONFIG_TEGRA20)
  150. #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
  151. FUNCMUX_UART1_UAA_UAB,
  152. #elif defined(CONFIG_TEGRA_UARTA_GPU)
  153. FUNCMUX_UART1_GPU,
  154. #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
  155. FUNCMUX_UART1_SDIO1,
  156. #else
  157. FUNCMUX_UART1_IRRX_IRTX,
  158. #endif
  159. FUNCMUX_UART2_UAD,
  160. -1,
  161. FUNCMUX_UART4_GMC,
  162. -1,
  163. #elif defined(CONFIG_TEGRA30)
  164. FUNCMUX_UART1_ULPI, /* UARTA */
  165. -1,
  166. -1,
  167. -1,
  168. -1,
  169. #elif defined(CONFIG_TEGRA114)
  170. -1,
  171. -1,
  172. -1,
  173. FUNCMUX_UART4_GMI, /* UARTD */
  174. -1,
  175. #elif defined(CONFIG_TEGRA124)
  176. FUNCMUX_UART1_KBC, /* UARTA */
  177. -1,
  178. -1,
  179. FUNCMUX_UART4_GPIO, /* UARTD */
  180. -1,
  181. #else /* Tegra210 */
  182. FUNCMUX_UART1_UART1, /* UARTA */
  183. -1,
  184. -1,
  185. FUNCMUX_UART4_UART4, /* UARTD */
  186. -1,
  187. #endif
  188. };
  189. /**
  190. * Set up the specified uarts
  191. *
  192. * @param uarts_ids Mask containing UARTs to init (UARTx)
  193. */
  194. static void setup_uarts(int uart_ids)
  195. {
  196. static enum periph_id id_for_uart[] = {
  197. PERIPH_ID_UART1,
  198. PERIPH_ID_UART2,
  199. PERIPH_ID_UART3,
  200. PERIPH_ID_UART4,
  201. PERIPH_ID_UART5,
  202. };
  203. size_t i;
  204. for (i = 0; i < UART_COUNT; i++) {
  205. if (uart_ids & (1 << i)) {
  206. enum periph_id id = id_for_uart[i];
  207. funcmux_select(id, uart_configs[i]);
  208. clock_ll_start_uart(id);
  209. }
  210. }
  211. }
  212. #endif
  213. void board_init_uart_f(void)
  214. {
  215. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  216. int uart_ids = 0; /* bit mask of which UART ids to enable */
  217. #ifdef CONFIG_TEGRA_ENABLE_UARTA
  218. uart_ids |= UARTA;
  219. #endif
  220. #ifdef CONFIG_TEGRA_ENABLE_UARTB
  221. uart_ids |= UARTB;
  222. #endif
  223. #ifdef CONFIG_TEGRA_ENABLE_UARTC
  224. uart_ids |= UARTC;
  225. #endif
  226. #ifdef CONFIG_TEGRA_ENABLE_UARTD
  227. uart_ids |= UARTD;
  228. #endif
  229. #ifdef CONFIG_TEGRA_ENABLE_UARTE
  230. uart_ids |= UARTE;
  231. #endif
  232. setup_uarts(uart_ids);
  233. #endif
  234. }
  235. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  236. static struct ns16550_plat ns16550_com1_pdata = {
  237. .base = CONFIG_SYS_NS16550_COM1,
  238. .reg_shift = 2,
  239. .clock = CONFIG_SYS_NS16550_CLK,
  240. .fcr = UART_FCR_DEFVAL,
  241. };
  242. U_BOOT_DRVINFO(ns16550_com1) = {
  243. "ns16550_serial", &ns16550_com1_pdata
  244. };
  245. #endif
  246. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  247. void enable_caches(void)
  248. {
  249. /* Enable D-cache. I-cache is already enabled in start.S */
  250. dcache_enable();
  251. }
  252. #endif