arm64-mmu.c 833 B

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. * (This file derived from arch/arm/mach-zynqmp/cpu.c)
  6. *
  7. * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
  8. */
  9. #include <common.h>
  10. #include <asm/system.h>
  11. #include <asm/armv8/mmu.h>
  12. /* size: IO + NR_DRAM_BANKS + terminator */
  13. struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
  14. {
  15. .virt = 0x0UL,
  16. .phys = 0x0UL,
  17. .size = 0x80000000UL,
  18. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  19. PTE_BLOCK_NON_SHARE |
  20. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  21. }, {
  22. .virt = 0x80000000UL,
  23. .phys = 0x80000000UL,
  24. .size = 0x80000000UL,
  25. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  26. PTE_BLOCK_INNER_SHARE
  27. }, {
  28. /* List terminator */
  29. 0,
  30. }
  31. };
  32. struct mm_region *mem_map = tegra_mem_map;