ap.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. /* Tegra AP (Application Processor) code */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <linux/bug.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/gp_padctrl.h>
  12. #include <asm/arch/mc.h>
  13. #include <asm/arch-tegra/ap.h>
  14. #include <asm/arch-tegra/clock.h>
  15. #include <asm/arch-tegra/fuse.h>
  16. #include <asm/arch-tegra/pmc.h>
  17. #include <asm/arch-tegra/scu.h>
  18. #include <asm/arch-tegra/tegra.h>
  19. #include <asm/arch-tegra/warmboot.h>
  20. int tegra_get_chip(void)
  21. {
  22. int rev;
  23. struct apb_misc_gp_ctlr *gp =
  24. (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
  25. /*
  26. * This is undocumented, Chip ID is bits 15:8 of the register
  27. * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
  28. * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
  29. */
  30. rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
  31. debug("%s: CHIPID is 0x%02X\n", __func__, rev);
  32. return rev;
  33. }
  34. int tegra_get_sku_info(void)
  35. {
  36. int sku_id;
  37. struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
  38. sku_id = readl(&fuse->sku_info) & 0xff;
  39. debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
  40. return sku_id;
  41. }
  42. int tegra_get_chip_sku(void)
  43. {
  44. uint sku_id, chip_id;
  45. chip_id = tegra_get_chip();
  46. sku_id = tegra_get_sku_info();
  47. switch (chip_id) {
  48. case CHIPID_TEGRA20:
  49. switch (sku_id) {
  50. case SKU_ID_T20_7:
  51. case SKU_ID_T20:
  52. return TEGRA_SOC_T20;
  53. case SKU_ID_T25SE:
  54. case SKU_ID_AP25:
  55. case SKU_ID_T25:
  56. case SKU_ID_AP25E:
  57. case SKU_ID_T25E:
  58. return TEGRA_SOC_T25;
  59. }
  60. break;
  61. case CHIPID_TEGRA30:
  62. switch (sku_id) {
  63. case SKU_ID_T33:
  64. case SKU_ID_T30:
  65. case SKU_ID_TM30MQS_P_A3:
  66. default:
  67. return TEGRA_SOC_T30;
  68. }
  69. break;
  70. case CHIPID_TEGRA114:
  71. switch (sku_id) {
  72. case SKU_ID_T114_ENG:
  73. case SKU_ID_T114_1:
  74. default:
  75. return TEGRA_SOC_T114;
  76. }
  77. break;
  78. case CHIPID_TEGRA124:
  79. switch (sku_id) {
  80. case SKU_ID_T124_ENG:
  81. default:
  82. return TEGRA_SOC_T124;
  83. }
  84. break;
  85. case CHIPID_TEGRA210:
  86. switch (sku_id) {
  87. case SKU_ID_T210_ENG:
  88. default:
  89. return TEGRA_SOC_T210;
  90. }
  91. break;
  92. }
  93. /* unknown chip/sku id */
  94. printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
  95. __func__, chip_id, sku_id);
  96. return TEGRA_SOC_UNKNOWN;
  97. }
  98. #ifndef CONFIG_ARM64
  99. static void enable_scu(void)
  100. {
  101. struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
  102. u32 reg;
  103. /* Only enable the SCU on T20/T25 */
  104. if (tegra_get_chip() != CHIPID_TEGRA20)
  105. return;
  106. /* If SCU already setup/enabled, return */
  107. if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
  108. return;
  109. /* Invalidate all ways for all processors */
  110. writel(0xFFFF, &scu->scu_inv_all);
  111. /* Enable SCU - bit 0 */
  112. reg = readl(&scu->scu_ctrl);
  113. reg |= SCU_CTRL_ENABLE;
  114. writel(reg, &scu->scu_ctrl);
  115. }
  116. static u32 get_odmdata(void)
  117. {
  118. /*
  119. * ODMDATA is stored in the BCT in IRAM by the BootROM.
  120. * The BCT start and size are stored in the BIT in IRAM.
  121. * Read the data @ bct_start + (bct_size - 12). This works
  122. * on BCTs for currently supported SoCs, which are locked down.
  123. * If this changes in new chips, we can revisit this algorithm.
  124. */
  125. unsigned long bct_start;
  126. u32 odmdata;
  127. bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
  128. odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
  129. return odmdata;
  130. }
  131. static void init_pmc_scratch(void)
  132. {
  133. struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  134. u32 odmdata;
  135. int i;
  136. /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
  137. #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  138. if (!tegra_cpu_is_non_secure())
  139. #endif
  140. {
  141. for (i = 0; i < 23; i++)
  142. writel(0, &pmc->pmc_scratch1 + i);
  143. }
  144. /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
  145. odmdata = get_odmdata();
  146. writel(odmdata, &pmc->pmc_scratch20);
  147. }
  148. #ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
  149. void protect_secure_section(void)
  150. {
  151. struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  152. /* Must be MB aligned */
  153. BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE & 0xFFFFF);
  154. BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE & 0xFFFFF);
  155. writel(CONFIG_ARMV7_SECURE_BASE, &mc->mc_security_cfg0);
  156. writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE >> 20, &mc->mc_security_cfg1);
  157. }
  158. #endif
  159. #if defined(CONFIG_ARMV7_NONSEC)
  160. static void smmu_flush(struct mc_ctlr *mc)
  161. {
  162. (void)readl(&mc->mc_smmu_config);
  163. }
  164. static void smmu_enable(void)
  165. {
  166. struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  167. u32 value;
  168. /*
  169. * Enable translation for all clients since access to this register
  170. * is restricted to TrustZone-secured requestors. The kernel will use
  171. * the per-SWGROUP enable bits to enable or disable translations.
  172. */
  173. writel(0xffffffff, &mc->mc_smmu_translation_enable_0);
  174. writel(0xffffffff, &mc->mc_smmu_translation_enable_1);
  175. writel(0xffffffff, &mc->mc_smmu_translation_enable_2);
  176. writel(0xffffffff, &mc->mc_smmu_translation_enable_3);
  177. /*
  178. * Enable SMMU globally since access to this register is restricted
  179. * to TrustZone-secured requestors.
  180. */
  181. value = readl(&mc->mc_smmu_config);
  182. value |= TEGRA_MC_SMMU_CONFIG_ENABLE;
  183. writel(value, &mc->mc_smmu_config);
  184. smmu_flush(mc);
  185. }
  186. #else
  187. static void smmu_enable(void)
  188. {
  189. }
  190. #endif
  191. void s_init(void)
  192. {
  193. /* Init PMC scratch memory */
  194. init_pmc_scratch();
  195. enable_scu();
  196. /* init the cache */
  197. config_cache();
  198. /* enable SMMU */
  199. smmu_enable();
  200. }
  201. #endif