reset_manager_arria10.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2017 Intel Corporation
  4. */
  5. #include <asm/global_data.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/fpga_manager.h>
  8. #include <asm/arch/misc.h>
  9. #include <asm/arch/reset_manager.h>
  10. #include <asm/arch/system_manager.h>
  11. #include <common.h>
  12. #include <errno.h>
  13. #include <fdtdec.h>
  14. #include <wait_bit.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. struct bridge_cfg {
  17. int compat_id;
  18. u32 mask_noc;
  19. u32 mask_rstmgr;
  20. };
  21. static const struct bridge_cfg bridge_cfg_tbl[] = {
  22. {
  23. COMPAT_ALTERA_SOCFPGA_H2F_BRG,
  24. ALT_SYSMGR_NOC_H2F_SET_MSK,
  25. ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
  26. },
  27. {
  28. COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
  29. ALT_SYSMGR_NOC_LWH2F_SET_MSK,
  30. ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
  31. },
  32. {
  33. COMPAT_ALTERA_SOCFPGA_F2H_BRG,
  34. ALT_SYSMGR_NOC_F2H_SET_MSK,
  35. ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
  36. },
  37. {
  38. COMPAT_ALTERA_SOCFPGA_F2SDR0,
  39. ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
  40. ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
  41. },
  42. {
  43. COMPAT_ALTERA_SOCFPGA_F2SDR1,
  44. ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
  45. ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
  46. },
  47. {
  48. COMPAT_ALTERA_SOCFPGA_F2SDR2,
  49. ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
  50. ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
  51. },
  52. };
  53. /* Disable the watchdog (toggle reset to watchdog) */
  54. void socfpga_watchdog_disable(void)
  55. {
  56. /* assert reset for watchdog */
  57. setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
  58. ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
  59. }
  60. /* Release NOC ddr scheduler from reset */
  61. void socfpga_reset_deassert_noc_ddr_scheduler(void)
  62. {
  63. clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
  64. ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
  65. }
  66. static int get_bridge_init_val(const void *blob, int compat_id)
  67. {
  68. int node;
  69. node = fdtdec_next_compatible(blob, 0, compat_id);
  70. if (node < 0)
  71. return 0;
  72. return fdtdec_get_uint(blob, node, "init-val", 0);
  73. }
  74. /* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
  75. int socfpga_reset_deassert_bridges_handoff(void)
  76. {
  77. u32 mask_noc = 0, mask_rstmgr = 0;
  78. int i;
  79. for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
  80. if (get_bridge_init_val(gd->fdt_blob,
  81. bridge_cfg_tbl[i].compat_id)) {
  82. mask_noc |= bridge_cfg_tbl[i].mask_noc;
  83. mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
  84. }
  85. }
  86. /* clear idle request to all bridges */
  87. setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_CLR,
  88. mask_noc);
  89. /* Release bridges from reset state per handoff value */
  90. clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
  91. mask_rstmgr);
  92. /* Poll until all idleack to 0, timeout at 1000ms */
  93. return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
  94. SYSMGR_A10_NOC_IDLEACK),
  95. mask_noc, false, 1000, false);
  96. }
  97. /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
  98. void socfpga_reset_deassert_osc1wd0(void)
  99. {
  100. clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
  101. ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
  102. }
  103. /*
  104. * Assert or de-assert SoCFPGA reset manager reset.
  105. */
  106. void socfpga_per_reset(u32 reset, int set)
  107. {
  108. unsigned long reg;
  109. u32 rstmgr_bank = RSTMGR_BANK(reset);
  110. switch (rstmgr_bank) {
  111. case 0:
  112. reg = RSTMGR_A10_MPUMODRST;
  113. break;
  114. case 1:
  115. reg = RSTMGR_A10_PER0MODRST;
  116. break;
  117. case 2:
  118. reg = RSTMGR_A10_PER1MODRST;
  119. break;
  120. case 3:
  121. reg = RSTMGR_A10_BRGMODRST;
  122. break;
  123. case 4:
  124. reg = RSTMGR_A10_SYSMODRST;
  125. break;
  126. default:
  127. return;
  128. }
  129. if (set)
  130. setbits_le32(socfpga_get_rstmgr_addr() + reg,
  131. 1 << RSTMGR_RESET(reset));
  132. else
  133. clrbits_le32(socfpga_get_rstmgr_addr() + reg,
  134. 1 << RSTMGR_RESET(reset));
  135. }
  136. /*
  137. * Assert reset on every peripheral but L4WD0.
  138. * Watchdog must be kept intact to prevent glitches
  139. * and/or hangs.
  140. * For the Arria10, we disable all the peripherals except L4 watchdog0,
  141. * L4 Timer 0, and ECC.
  142. */
  143. void socfpga_per_reset_all(void)
  144. {
  145. const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
  146. (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
  147. unsigned mask_ecc_ocp =
  148. ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
  149. ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
  150. ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
  151. ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
  152. ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
  153. ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
  154. ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
  155. ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
  156. /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
  157. writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST);
  158. setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
  159. ~mask_ecc_ocp);
  160. /* Finally disable the ECC_OCP */
  161. setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
  162. mask_ecc_ocp);
  163. }
  164. int socfpga_bridges_reset(void)
  165. {
  166. int ret;
  167. /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
  168. fpga2sdram) */
  169. /* set idle request to all bridges */
  170. writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
  171. ALT_SYSMGR_NOC_LWH2F_SET_MSK |
  172. ALT_SYSMGR_NOC_F2H_SET_MSK |
  173. ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
  174. ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
  175. ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
  176. socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_SET);
  177. /* Enable the NOC timeout */
  178. writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK,
  179. socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
  180. /* Poll until all idleack to 1 */
  181. ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
  182. SYSMGR_A10_NOC_IDLEACK),
  183. ALT_SYSMGR_NOC_H2F_SET_MSK |
  184. ALT_SYSMGR_NOC_LWH2F_SET_MSK |
  185. ALT_SYSMGR_NOC_F2H_SET_MSK |
  186. ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
  187. ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
  188. ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
  189. true, 10000, false);
  190. if (ret)
  191. return ret;
  192. /* Poll until all idlestatus to 1 */
  193. ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
  194. SYSMGR_A10_NOC_IDLESTATUS),
  195. ALT_SYSMGR_NOC_H2F_SET_MSK |
  196. ALT_SYSMGR_NOC_LWH2F_SET_MSK |
  197. ALT_SYSMGR_NOC_F2H_SET_MSK |
  198. ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
  199. ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
  200. ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
  201. true, 10000, false);
  202. if (ret)
  203. return ret;
  204. /* Put all bridges (except NOR DDR scheduler) into reset state */
  205. setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
  206. (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
  207. ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
  208. ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
  209. ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
  210. ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
  211. ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
  212. /* Disable NOC timeout */
  213. writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
  214. return 0;
  215. }