omap-cache.c 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Common functions for OMAP4/5 based boards
  5. *
  6. * (C) Copyright 2010
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Author :
  10. * Aneesh V <aneesh@ti.com>
  11. * Steve Sakoman <steve@sakoman.com>
  12. */
  13. #include <common.h>
  14. #include <cpu_func.h>
  15. #include <log.h>
  16. #include <asm/cache.h>
  17. #include <asm/global_data.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /*
  20. * Without LPAE short descriptors are used
  21. * Set C - Cache Bit3
  22. * Set B - Buffer Bit2
  23. * The last 2 bits set to 0b10
  24. * Do Not set XN bit4
  25. * So value is 0xe
  26. *
  27. * With LPAE cache configuration happens via MAIR0 register
  28. * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
  29. * 0xFF maps to Cache writeback with Read and Write Allocate set
  30. * The bits[1:0] should have the value 0b01 for the first level
  31. * descriptor.
  32. * So the value is 0xd
  33. */
  34. #ifdef CONFIG_ARMV7_LPAE
  35. #define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
  36. #else
  37. #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
  38. #endif
  39. void enable_caches(void)
  40. {
  41. /* Enable I cache if not enabled */
  42. if (!icache_status())
  43. icache_enable();
  44. dcache_enable();
  45. }
  46. void dram_bank_mmu_setup(int bank)
  47. {
  48. struct bd_info *bd = gd->bd;
  49. int i;
  50. u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
  51. u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
  52. u32 end = start + size;
  53. debug("%s: bank: %d\n", __func__, bank);
  54. for (i = start; i < end; i++)
  55. set_section_dcache(i, ARMV7_DCACHE_POLICY);
  56. }