mem-common.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Texas Instruments, <www.ti.com>
  5. *
  6. * Author :
  7. * Mansoor Ahamed <mansoor.ahamed@ti.com>
  8. *
  9. * Initial Code from:
  10. * Manikandan Pillai <mani.pillai@ti.com>
  11. * Richard Woodruff <r-woodruff2@ti.com>
  12. * Syed Mohammed Khasim <khasim@ti.com>
  13. */
  14. #include <common.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/cpu.h>
  17. #if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN)
  18. #include <asm/arch/mem-guardian.h>
  19. #else
  20. #include <asm/arch/mem.h>
  21. #endif
  22. #include <asm/arch/sys_proto.h>
  23. #include <command.h>
  24. #include <linux/mtd/omap_gpmc.h>
  25. #include <jffs2/load_kernel.h>
  26. const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
  27. #if defined(CONFIG_NOR)
  28. char gpmc_cs0_flash = MTD_DEV_TYPE_NOR;
  29. #elif defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
  30. char gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  31. #elif defined(CONFIG_CMD_ONENAND)
  32. char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  33. #else
  34. char gpmc_cs0_flash = -1;
  35. #endif
  36. #if defined(CONFIG_OMAP34XX)
  37. /********************************************************
  38. * mem_ok() - test used to see if timings are correct
  39. * for a part. Helps in guessing which part
  40. * we are currently using.
  41. *******************************************************/
  42. u32 mem_ok(u32 cs)
  43. {
  44. u32 val1, val2, addr;
  45. u32 pattern = 0x12345678;
  46. addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
  47. writel(0x0, addr + 0x400); /* clear pos A */
  48. writel(pattern, addr); /* pattern to pos B */
  49. writel(0x0, addr + 4); /* remove pattern off the bus */
  50. val1 = readl(addr + 0x400); /* get pos A value */
  51. val2 = readl(addr); /* get val2 */
  52. writel(0x0, addr + 0x400); /* clear pos A */
  53. if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
  54. return 0;
  55. else
  56. return 1;
  57. }
  58. #endif
  59. void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
  60. u32 base, u32 size)
  61. {
  62. writel(0, &cs->config7);
  63. sdelay(1000);
  64. /* Delay for settling */
  65. writel(gpmc_config[0], &cs->config1);
  66. writel(gpmc_config[1], &cs->config2);
  67. writel(gpmc_config[2], &cs->config3);
  68. writel(gpmc_config[3], &cs->config4);
  69. writel(gpmc_config[4], &cs->config5);
  70. writel(gpmc_config[5], &cs->config6);
  71. /* Enable the config */
  72. writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
  73. (1 << 6)), &cs->config7);
  74. sdelay(2000);
  75. }
  76. void set_gpmc_cs0(int flash_type)
  77. {
  78. const u32 *gpmc_regs;
  79. u32 base, size;
  80. #if defined(CONFIG_NOR)
  81. const u32 gpmc_regs_nor[GPMC_MAX_REG] = {
  82. STNOR_GPMC_CONFIG1,
  83. STNOR_GPMC_CONFIG2,
  84. STNOR_GPMC_CONFIG3,
  85. STNOR_GPMC_CONFIG4,
  86. STNOR_GPMC_CONFIG5,
  87. STNOR_GPMC_CONFIG6,
  88. STNOR_GPMC_CONFIG7
  89. };
  90. #endif
  91. #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
  92. const u32 gpmc_regs_nand[GPMC_MAX_REG] = {
  93. M_NAND_GPMC_CONFIG1,
  94. M_NAND_GPMC_CONFIG2,
  95. M_NAND_GPMC_CONFIG3,
  96. M_NAND_GPMC_CONFIG4,
  97. M_NAND_GPMC_CONFIG5,
  98. M_NAND_GPMC_CONFIG6,
  99. 0
  100. };
  101. #endif
  102. #if defined(CONFIG_CMD_ONENAND)
  103. const u32 gpmc_regs_onenand[GPMC_MAX_REG] = {
  104. ONENAND_GPMC_CONFIG1,
  105. ONENAND_GPMC_CONFIG2,
  106. ONENAND_GPMC_CONFIG3,
  107. ONENAND_GPMC_CONFIG4,
  108. ONENAND_GPMC_CONFIG5,
  109. ONENAND_GPMC_CONFIG6,
  110. 0
  111. };
  112. #endif
  113. switch (flash_type) {
  114. #if defined(CONFIG_NOR)
  115. case MTD_DEV_TYPE_NOR:
  116. gpmc_regs = gpmc_regs_nor;
  117. base = CONFIG_SYS_FLASH_BASE;
  118. size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
  119. ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
  120. ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
  121. ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
  122. GPMC_SIZE_16M)));
  123. break;
  124. #endif
  125. #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
  126. case MTD_DEV_TYPE_NAND:
  127. gpmc_regs = gpmc_regs_nand;
  128. base = CONFIG_SYS_NAND_BASE;
  129. size = GPMC_SIZE_16M;
  130. break;
  131. #endif
  132. #if defined(CONFIG_CMD_ONENAND)
  133. case MTD_DEV_TYPE_ONENAND:
  134. gpmc_regs = gpmc_regs_onenand;
  135. base = CONFIG_SYS_ONENAND_BASE;
  136. size = GPMC_SIZE_128M;
  137. break;
  138. #endif
  139. default:
  140. /* disable the GPMC0 config set by ROM code */
  141. writel(0, &gpmc_cfg->cs[0].config7);
  142. sdelay(1000);
  143. return;
  144. }
  145. /* enable chip-select specific configurations */
  146. enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
  147. }
  148. /*****************************************************
  149. * gpmc_init(): init gpmc bus
  150. * Init GPMC for x16, MuxMode (SDRAM in x32).
  151. * This code can only be executed from SRAM or SDRAM.
  152. *****************************************************/
  153. void gpmc_init(void)
  154. {
  155. /* global settings */
  156. writel(0x00000008, &gpmc_cfg->sysconfig);
  157. writel(0x00000000, &gpmc_cfg->irqstatus);
  158. writel(0x00000000, &gpmc_cfg->irqenable);
  159. /* disable timeout, set a safe reset value */
  160. writel(0x00001ff0, &gpmc_cfg->timeout_control);
  161. writel(gpmc_cs0_flash == MTD_DEV_TYPE_NOR ?
  162. 0x00000200 : 0x00000012, &gpmc_cfg->config);
  163. set_gpmc_cs0(gpmc_cs0_flash);
  164. }