tpm-v2.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Defines APIs and structures that allow software to interact with a
  4. * TPM2 device
  5. *
  6. * Copyright (c) 2020 Linaro
  7. * Copyright (c) 2018 Bootlin
  8. *
  9. * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
  10. *
  11. * Author: Miquel Raynal <miquel.raynal@bootlin.com>
  12. */
  13. #ifndef __TPM_V2_H
  14. #define __TPM_V2_H
  15. #include <tpm-common.h>
  16. struct udevice;
  17. #define TPM2_DIGEST_LEN 32
  18. #define TPM2_SHA1_DIGEST_SIZE 20
  19. #define TPM2_SHA256_DIGEST_SIZE 32
  20. #define TPM2_SHA384_DIGEST_SIZE 48
  21. #define TPM2_SHA512_DIGEST_SIZE 64
  22. #define TPM2_SM3_256_DIGEST_SIZE 32
  23. #define TPM2_MAX_PCRS 32
  24. #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
  25. #define TPM2_MAX_CAP_BUFFER 1024
  26. #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
  27. sizeof(u32)) / sizeof(struct tpms_tagged_property))
  28. #define TPM2_HDR_LEN 10
  29. /*
  30. * We deviate from this draft of the specification by increasing the value of
  31. * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
  32. * implementations that have enabled a larger than typical number of PCR
  33. * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
  34. * in a future revision of the specification.
  35. */
  36. #define TPM2_NUM_PCR_BANKS 16
  37. /* Definition of (UINT32) TPM2_CAP Constants */
  38. #define TPM2_CAP_PCRS 0x00000005U
  39. #define TPM2_CAP_TPM_PROPERTIES 0x00000006U
  40. /* Definition of (UINT32) TPM2_PT Constants */
  41. #define TPM2_PT_GROUP (u32)(0x00000100)
  42. #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
  43. #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
  44. #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
  45. #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
  46. #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
  47. /*
  48. * event types, cf.
  49. * "TCG Server Management Domain Firmware Profile Specification",
  50. * rev 1.00, 2020-05-01
  51. */
  52. #define EV_POST_CODE ((u32)0x00000001)
  53. #define EV_NO_ACTION ((u32)0x00000003)
  54. #define EV_SEPARATOR ((u32)0x00000004)
  55. #define EV_ACTION ((u32)0x00000005)
  56. #define EV_TAG ((u32)0x00000006)
  57. #define EV_S_CRTM_CONTENTS ((u32)0x00000007)
  58. #define EV_S_CRTM_VERSION ((u32)0x00000008)
  59. #define EV_CPU_MICROCODE ((u32)0x00000009)
  60. #define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
  61. #define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
  62. #define EV_COMPACT_HASH ((u32)0x0000000C)
  63. /*
  64. * event types, cf.
  65. * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
  66. * Level 00 Version 1.05 Revision 23, May 7, 2021
  67. */
  68. #define EV_EFI_EVENT_BASE ((u32)0x80000000)
  69. #define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001)
  70. #define EV_EFI_VARIABLE_BOOT ((u32)0x80000002)
  71. #define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003)
  72. #define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004)
  73. #define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005)
  74. #define EV_EFI_GPT_EVENT ((u32)0x80000006)
  75. #define EV_EFI_ACTION ((u32)0x80000007)
  76. #define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008)
  77. #define EV_EFI_HANDOFF_TABLES ((u32)0x80000009)
  78. #define EV_EFI_PLATFORM_FIRMWARE_BLOB2 ((u32)0x8000000A)
  79. #define EV_EFI_HANDOFF_TABLES2 ((u32)0x8000000B)
  80. #define EV_EFI_VARIABLE_BOOT2 ((u32)0x8000000C)
  81. #define EV_EFI_HCRTM_EVENT ((u32)0x80000010)
  82. #define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0)
  83. #define EV_EFI_SPDM_FIRMWARE_BLOB ((u32)0x800000E1)
  84. #define EV_EFI_SPDM_FIRMWARE_CONFIG ((u32)0x800000E2)
  85. #define EFI_CALLING_EFI_APPLICATION \
  86. "Calling EFI Application from Boot Option"
  87. #define EFI_RETURNING_FROM_EFI_APPLICATION \
  88. "Returning from EFI Application from Boot Option"
  89. #define EFI_EXIT_BOOT_SERVICES_INVOCATION \
  90. "Exit Boot Services Invocation"
  91. #define EFI_EXIT_BOOT_SERVICES_FAILED \
  92. "Exit Boot Services Returned with Failure"
  93. #define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \
  94. "Exit Boot Services Returned with Success"
  95. /* TPMS_TAGGED_PROPERTY Structure */
  96. struct tpms_tagged_property {
  97. u32 property;
  98. u32 value;
  99. } __packed;
  100. /* TPMS_PCR_SELECTION Structure */
  101. struct tpms_pcr_selection {
  102. u16 hash;
  103. u8 size_of_select;
  104. u8 pcr_select[TPM2_PCR_SELECT_MAX];
  105. } __packed;
  106. /* TPML_PCR_SELECTION Structure */
  107. struct tpml_pcr_selection {
  108. u32 count;
  109. struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
  110. } __packed;
  111. /* TPML_TAGGED_TPM_PROPERTY Structure */
  112. struct tpml_tagged_tpm_property {
  113. u32 count;
  114. struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
  115. } __packed;
  116. /* TPMU_CAPABILITIES Union */
  117. union tpmu_capabilities {
  118. /*
  119. * Non exhaustive. Only added the structs needed for our
  120. * current code
  121. */
  122. struct tpml_pcr_selection assigned_pcr;
  123. struct tpml_tagged_tpm_property tpm_properties;
  124. } __packed;
  125. /* TPMS_CAPABILITY_DATA Structure */
  126. struct tpms_capability_data {
  127. u32 capability;
  128. union tpmu_capabilities data;
  129. } __packed;
  130. /**
  131. * SHA1 Event Log Entry Format
  132. *
  133. * @pcr_index: PCRIndex event extended to
  134. * @event_type: Type of event (see EFI specs)
  135. * @digest: Value extended into PCR index
  136. * @event_size: Size of event
  137. * @event: Event data
  138. */
  139. struct tcg_pcr_event {
  140. u32 pcr_index;
  141. u32 event_type;
  142. u8 digest[TPM2_SHA1_DIGEST_SIZE];
  143. u32 event_size;
  144. u8 event[];
  145. } __packed;
  146. /**
  147. * Definition of TPMU_HA Union
  148. */
  149. union tmpu_ha {
  150. u8 sha1[TPM2_SHA1_DIGEST_SIZE];
  151. u8 sha256[TPM2_SHA256_DIGEST_SIZE];
  152. u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
  153. u8 sha384[TPM2_SHA384_DIGEST_SIZE];
  154. u8 sha512[TPM2_SHA512_DIGEST_SIZE];
  155. } __packed;
  156. /**
  157. * Definition of TPMT_HA Structure
  158. *
  159. * @hash_alg: Hash algorithm defined in enum tpm2_algorithms
  160. * @digest: Digest value for a given algorithm
  161. */
  162. struct tpmt_ha {
  163. u16 hash_alg;
  164. union tmpu_ha digest;
  165. } __packed;
  166. /**
  167. * Definition of TPML_DIGEST_VALUES Structure
  168. *
  169. * @count: Number of algorithms supported by hardware
  170. * @digests: struct for algorithm id and hash value
  171. */
  172. struct tpml_digest_values {
  173. u32 count;
  174. struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
  175. } __packed;
  176. /**
  177. * Crypto Agile Log Entry Format
  178. *
  179. * @pcr_index: PCRIndex event extended to
  180. * @event_type: Type of event
  181. * @digests: List of digestsextended to PCR index
  182. * @event_size: Size of the event data
  183. * @event: Event data
  184. */
  185. struct tcg_pcr_event2 {
  186. u32 pcr_index;
  187. u32 event_type;
  188. struct tpml_digest_values digests;
  189. u32 event_size;
  190. u8 event[];
  191. } __packed;
  192. /**
  193. * TPM2 Structure Tags for command/response buffers.
  194. *
  195. * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
  196. * @TPM2_ST_SESSIONS: the command needs an authentication.
  197. */
  198. enum tpm2_structures {
  199. TPM2_ST_NO_SESSIONS = 0x8001,
  200. TPM2_ST_SESSIONS = 0x8002,
  201. };
  202. /**
  203. * TPM2 type of boolean.
  204. */
  205. enum tpm2_yes_no {
  206. TPMI_YES = 1,
  207. TPMI_NO = 0,
  208. };
  209. /**
  210. * TPM2 startup values.
  211. *
  212. * @TPM2_SU_CLEAR: reset the internal state.
  213. * @TPM2_SU_STATE: restore saved state (if any).
  214. */
  215. enum tpm2_startup_types {
  216. TPM2_SU_CLEAR = 0x0000,
  217. TPM2_SU_STATE = 0x0001,
  218. };
  219. /**
  220. * TPM2 permanent handles.
  221. *
  222. * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
  223. * @TPM2_RS_PW: indicates a password.
  224. * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
  225. * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
  226. * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
  227. */
  228. enum tpm2_handles {
  229. TPM2_RH_OWNER = 0x40000001,
  230. TPM2_RS_PW = 0x40000009,
  231. TPM2_RH_LOCKOUT = 0x4000000A,
  232. TPM2_RH_ENDORSEMENT = 0x4000000B,
  233. TPM2_RH_PLATFORM = 0x4000000C,
  234. };
  235. /**
  236. * TPM2 command codes used at the beginning of a buffer, gives the command.
  237. *
  238. * @TPM2_CC_STARTUP: TPM2_Startup().
  239. * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
  240. * @TPM2_CC_CLEAR: TPM2_Clear().
  241. * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
  242. * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
  243. * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
  244. * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
  245. * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
  246. * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
  247. * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
  248. * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
  249. * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
  250. * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
  251. */
  252. enum tpm2_command_codes {
  253. TPM2_CC_STARTUP = 0x0144,
  254. TPM2_CC_SELF_TEST = 0x0143,
  255. TPM2_CC_HIER_CONTROL = 0x0121,
  256. TPM2_CC_CLEAR = 0x0126,
  257. TPM2_CC_CLEARCONTROL = 0x0127,
  258. TPM2_CC_HIERCHANGEAUTH = 0x0129,
  259. TPM2_CC_NV_DEFINE_SPACE = 0x012a,
  260. TPM2_CC_PCR_SETAUTHPOL = 0x012C,
  261. TPM2_CC_NV_WRITE = 0x0137,
  262. TPM2_CC_NV_WRITELOCK = 0x0138,
  263. TPM2_CC_DAM_RESET = 0x0139,
  264. TPM2_CC_DAM_PARAMETERS = 0x013A,
  265. TPM2_CC_NV_READ = 0x014E,
  266. TPM2_CC_GET_CAPABILITY = 0x017A,
  267. TPM2_CC_GET_RANDOM = 0x017B,
  268. TPM2_CC_PCR_READ = 0x017E,
  269. TPM2_CC_PCR_EXTEND = 0x0182,
  270. TPM2_CC_PCR_SETAUTHVAL = 0x0183,
  271. };
  272. /**
  273. * TPM2 return codes.
  274. */
  275. enum tpm2_return_codes {
  276. TPM2_RC_SUCCESS = 0x0000,
  277. TPM2_RC_BAD_TAG = 0x001E,
  278. TPM2_RC_FMT1 = 0x0080,
  279. TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
  280. TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
  281. TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
  282. TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
  283. TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
  284. TPM2_RC_VER1 = 0x0100,
  285. TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
  286. TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
  287. TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
  288. TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
  289. TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
  290. TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
  291. TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
  292. TPM2_RC_NV_DEFINED = TPM2_RC_VER1 + 0x004c,
  293. TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
  294. TPM2_RC_WARN = 0x0900,
  295. TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
  296. TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
  297. TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
  298. };
  299. /**
  300. * TPM2 algorithms.
  301. */
  302. enum tpm2_algorithms {
  303. TPM2_ALG_SHA1 = 0x04,
  304. TPM2_ALG_XOR = 0x0A,
  305. TPM2_ALG_SHA256 = 0x0B,
  306. TPM2_ALG_SHA384 = 0x0C,
  307. TPM2_ALG_SHA512 = 0x0D,
  308. TPM2_ALG_NULL = 0x10,
  309. TPM2_ALG_SM3_256 = 0x12,
  310. };
  311. /* NV index attributes */
  312. enum tpm_index_attrs {
  313. TPMA_NV_PPWRITE = 1UL << 0,
  314. TPMA_NV_OWNERWRITE = 1UL << 1,
  315. TPMA_NV_AUTHWRITE = 1UL << 2,
  316. TPMA_NV_POLICYWRITE = 1UL << 3,
  317. TPMA_NV_COUNTER = 1UL << 4,
  318. TPMA_NV_BITS = 1UL << 5,
  319. TPMA_NV_EXTEND = 1UL << 6,
  320. TPMA_NV_POLICY_DELETE = 1UL << 10,
  321. TPMA_NV_WRITELOCKED = 1UL << 11,
  322. TPMA_NV_WRITEALL = 1UL << 12,
  323. TPMA_NV_WRITEDEFINE = 1UL << 13,
  324. TPMA_NV_WRITE_STCLEAR = 1UL << 14,
  325. TPMA_NV_GLOBALLOCK = 1UL << 15,
  326. TPMA_NV_PPREAD = 1UL << 16,
  327. TPMA_NV_OWNERREAD = 1UL << 17,
  328. TPMA_NV_AUTHREAD = 1UL << 18,
  329. TPMA_NV_POLICYREAD = 1UL << 19,
  330. TPMA_NV_NO_DA = 1UL << 25,
  331. TPMA_NV_ORDERLY = 1UL << 26,
  332. TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
  333. TPMA_NV_READLOCKED = 1UL << 28,
  334. TPMA_NV_WRITTEN = 1UL << 29,
  335. TPMA_NV_PLATFORMCREATE = 1UL << 30,
  336. TPMA_NV_READ_STCLEAR = 1UL << 31,
  337. TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
  338. TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
  339. TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
  340. TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
  341. };
  342. enum {
  343. TPM_ACCESS_VALID = 1 << 7,
  344. TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
  345. TPM_ACCESS_REQUEST_PENDING = 1 << 2,
  346. TPM_ACCESS_REQUEST_USE = 1 << 1,
  347. TPM_ACCESS_ESTABLISHMENT = 1 << 0,
  348. };
  349. enum {
  350. TPM_STS_FAMILY_SHIFT = 26,
  351. TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
  352. TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
  353. TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
  354. TPM_STS_COMMAND_CANCEL = 1 << 24,
  355. TPM_STS_BURST_COUNT_SHIFT = 8,
  356. TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
  357. TPM_STS_VALID = 1 << 7,
  358. TPM_STS_COMMAND_READY = 1 << 6,
  359. TPM_STS_GO = 1 << 5,
  360. TPM_STS_DATA_AVAIL = 1 << 4,
  361. TPM_STS_DATA_EXPECT = 1 << 3,
  362. TPM_STS_SELF_TEST_DONE = 1 << 2,
  363. TPM_STS_RESPONSE_RETRY = 1 << 1,
  364. TPM_STS_READ_ZERO = 0x23
  365. };
  366. enum {
  367. TPM_CMD_COUNT_OFFSET = 2,
  368. TPM_CMD_ORDINAL_OFFSET = 6,
  369. TPM_MAX_BUF_SIZE = 1260,
  370. };
  371. enum {
  372. /* Secure storage for firmware settings */
  373. TPM_HT_PCR = 0,
  374. TPM_HT_NV_INDEX,
  375. TPM_HT_HMAC_SESSION,
  376. TPM_HT_POLICY_SESSION,
  377. HR_SHIFT = 24,
  378. HR_PCR = TPM_HT_PCR << HR_SHIFT,
  379. HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT,
  380. HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT,
  381. HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT,
  382. };
  383. /**
  384. * Issue a TPM2_Startup command.
  385. *
  386. * @dev TPM device
  387. * @mode TPM startup mode
  388. *
  389. * Return: code of the operation
  390. */
  391. u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
  392. /**
  393. * Issue a TPM2_SelfTest command.
  394. *
  395. * @dev TPM device
  396. * @full_test Asking to perform all tests or only the untested ones
  397. *
  398. * Return: code of the operation
  399. */
  400. u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
  401. /**
  402. * Issue a TPM2_Clear command.
  403. *
  404. * @dev TPM device
  405. * @handle Handle
  406. * @pw Password
  407. * @pw_sz Length of the password
  408. *
  409. * Return: code of the operation
  410. */
  411. u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
  412. const ssize_t pw_sz);
  413. /**
  414. * Issue a TPM_NV_DefineSpace command
  415. *
  416. * This allows a space to be defined with given attributes and policy
  417. *
  418. * @dev TPM device
  419. * @space_index index of the area
  420. * @space_size size of area in bytes
  421. * @nv_attributes TPM_NV_ATTRIBUTES of the area
  422. * @nv_policy policy to use
  423. * @nv_policy_size size of the policy
  424. * Return: return code of the operation
  425. */
  426. u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
  427. size_t space_size, u32 nv_attributes,
  428. const u8 *nv_policy, size_t nv_policy_size);
  429. /**
  430. * Issue a TPM2_PCR_Extend command.
  431. *
  432. * @dev TPM device
  433. * @index Index of the PCR
  434. * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
  435. * @digest Value representing the event to be recorded
  436. * @digest_len len of the hash
  437. *
  438. * Return: code of the operation
  439. */
  440. u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
  441. const u8 *digest, u32 digest_len);
  442. /**
  443. * Read data from the secure storage
  444. *
  445. * @dev TPM device
  446. * @index Index of data to read
  447. * @data Place to put data
  448. * @count Number of bytes of data
  449. * Return: code of the operation
  450. */
  451. u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
  452. /**
  453. * Write data to the secure storage
  454. *
  455. * @dev TPM device
  456. * @index Index of data to write
  457. * @data Data to write
  458. * @count Number of bytes of data
  459. * Return: code of the operation
  460. */
  461. u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
  462. u32 count);
  463. /**
  464. * Issue a TPM2_PCR_Read command.
  465. *
  466. * @dev TPM device
  467. * @idx Index of the PCR
  468. * @idx_min_sz Minimum size in bytes of the pcrSelect array
  469. * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
  470. * @data Output buffer for contents of the named PCR
  471. * @digest_len len of the data
  472. * @updates Optional out parameter: number of updates for this PCR
  473. *
  474. * Return: code of the operation
  475. */
  476. u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
  477. u16 algorithm, void *data, u32 digest_len,
  478. unsigned int *updates);
  479. /**
  480. * Issue a TPM2_GetCapability command. This implementation is limited
  481. * to query property index that is 4-byte wide.
  482. *
  483. * @dev TPM device
  484. * @capability Partition of capabilities
  485. * @property Further definition of capability, limited to be 4 bytes wide
  486. * @buf Output buffer for capability information
  487. * @prop_count Size of output buffer
  488. *
  489. * Return: code of the operation
  490. */
  491. u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
  492. void *buf, size_t prop_count);
  493. /**
  494. * Issue a TPM2_DictionaryAttackLockReset command.
  495. *
  496. * @dev TPM device
  497. * @pw Password
  498. * @pw_sz Length of the password
  499. *
  500. * Return: code of the operation
  501. */
  502. u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
  503. /**
  504. * Issue a TPM2_DictionaryAttackParameters command.
  505. *
  506. * @dev TPM device
  507. * @pw Password
  508. * @pw_sz Length of the password
  509. * @max_tries Count of authorizations before lockout
  510. * @recovery_time Time before decrementation of the failure count
  511. * @lockout_recovery Time to wait after a lockout
  512. *
  513. * Return: code of the operation
  514. */
  515. u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
  516. const ssize_t pw_sz, unsigned int max_tries,
  517. unsigned int recovery_time,
  518. unsigned int lockout_recovery);
  519. /**
  520. * Issue a TPM2_HierarchyChangeAuth command.
  521. *
  522. * @dev TPM device
  523. * @handle Handle
  524. * @newpw New password
  525. * @newpw_sz Length of the new password
  526. * @oldpw Old password
  527. * @oldpw_sz Length of the old password
  528. *
  529. * Return: code of the operation
  530. */
  531. int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
  532. const ssize_t newpw_sz, const char *oldpw,
  533. const ssize_t oldpw_sz);
  534. /**
  535. * Issue a TPM_PCR_SetAuthPolicy command.
  536. *
  537. * @dev TPM device
  538. * @pw Platform password
  539. * @pw_sz Length of the password
  540. * @index Index of the PCR
  541. * @digest New key to access the PCR
  542. *
  543. * Return: code of the operation
  544. */
  545. u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
  546. const ssize_t pw_sz, u32 index, const char *key);
  547. /**
  548. * Issue a TPM_PCR_SetAuthValue command.
  549. *
  550. * @dev TPM device
  551. * @pw Platform password
  552. * @pw_sz Length of the password
  553. * @index Index of the PCR
  554. * @digest New key to access the PCR
  555. * @key_sz Length of the new key
  556. *
  557. * Return: code of the operation
  558. */
  559. u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
  560. const ssize_t pw_sz, u32 index, const char *key,
  561. const ssize_t key_sz);
  562. /**
  563. * Issue a TPM2_GetRandom command.
  564. *
  565. * @dev TPM device
  566. * @param data output buffer for the random bytes
  567. * @param count size of output buffer
  568. *
  569. * Return: return code of the operation
  570. */
  571. u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
  572. /**
  573. * Lock data in the TPM
  574. *
  575. * Once locked the data cannot be written until after a reboot
  576. *
  577. * @dev TPM device
  578. * @index Index of data to lock
  579. * Return: code of the operation
  580. */
  581. u32 tpm2_write_lock(struct udevice *dev, u32 index);
  582. /**
  583. * Disable access to any platform data
  584. *
  585. * This can be called to close off access to the firmware data in the data,
  586. * before calling the kernel.
  587. *
  588. * @dev TPM device
  589. * Return: code of the operation
  590. */
  591. u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
  592. /**
  593. * submit user specified data to the TPM and get response
  594. *
  595. * @dev TPM device
  596. * @sendbuf: Buffer of the data to send
  597. * @recvbuf: Buffer to save the response to
  598. * @recv_size: Pointer to the size of the response buffer
  599. *
  600. * Return: code of the operation
  601. */
  602. u32 tpm2_submit_command(struct udevice *dev, const u8 *sendbuf,
  603. u8 *recvbuf, size_t *recv_size);
  604. #endif /* __TPM_V2_H */