pci.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Andreas Heppel <aheppel@sysgo.de>
  5. *
  6. * (C) Copyright 2002
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
  9. */
  10. /*
  11. * PCI routines
  12. */
  13. #include <common.h>
  14. #include <bootretry.h>
  15. #include <cli.h>
  16. #include <command.h>
  17. #include <console.h>
  18. #include <dm.h>
  19. #include <init.h>
  20. #include <asm/processor.h>
  21. #include <asm/io.h>
  22. #include <pci.h>
  23. struct pci_reg_info {
  24. const char *name;
  25. enum pci_size_t size;
  26. u8 offset;
  27. };
  28. static int pci_byte_size(enum pci_size_t size)
  29. {
  30. switch (size) {
  31. case PCI_SIZE_8:
  32. return 1;
  33. case PCI_SIZE_16:
  34. return 2;
  35. case PCI_SIZE_32:
  36. default:
  37. return 4;
  38. }
  39. }
  40. static int pci_field_width(enum pci_size_t size)
  41. {
  42. return pci_byte_size(size) * 2;
  43. }
  44. static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
  45. {
  46. for (; regs->name; regs++) {
  47. unsigned long val;
  48. dm_pci_read_config(dev, regs->offset, &val, regs->size);
  49. printf(" %s =%*s%#.*lx\n", regs->name,
  50. (int)(28 - strlen(regs->name)), "",
  51. pci_field_width(regs->size), val);
  52. }
  53. }
  54. static int pci_bar_show(struct udevice *dev)
  55. {
  56. u8 header_type;
  57. int bar_cnt, bar_id, mem_type;
  58. bool is_64, is_io;
  59. u32 base_low, base_high;
  60. u32 size_low, size_high;
  61. u64 base, size;
  62. u32 reg_addr;
  63. int prefetchable;
  64. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  65. header_type &= 0x7f;
  66. if (header_type == PCI_HEADER_TYPE_CARDBUS) {
  67. printf("CardBus doesn't support BARs\n");
  68. return -ENOSYS;
  69. } else if (header_type != PCI_HEADER_TYPE_NORMAL &&
  70. header_type != PCI_HEADER_TYPE_BRIDGE) {
  71. printf("unknown header type\n");
  72. return -ENOSYS;
  73. }
  74. bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
  75. printf("ID Base Size Width Type\n");
  76. printf("----------------------------------------------------------\n");
  77. bar_id = 0;
  78. reg_addr = PCI_BASE_ADDRESS_0;
  79. while (bar_cnt) {
  80. dm_pci_read_config32(dev, reg_addr, &base_low);
  81. dm_pci_write_config32(dev, reg_addr, 0xffffffff);
  82. dm_pci_read_config32(dev, reg_addr, &size_low);
  83. dm_pci_write_config32(dev, reg_addr, base_low);
  84. reg_addr += 4;
  85. base = base_low & ~0xf;
  86. size = size_low & ~0xf;
  87. base_high = 0x0;
  88. size_high = 0xffffffff;
  89. is_64 = 0;
  90. prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
  91. is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
  92. mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  93. if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
  94. dm_pci_read_config32(dev, reg_addr, &base_high);
  95. dm_pci_write_config32(dev, reg_addr, 0xffffffff);
  96. dm_pci_read_config32(dev, reg_addr, &size_high);
  97. dm_pci_write_config32(dev, reg_addr, base_high);
  98. bar_cnt--;
  99. reg_addr += 4;
  100. is_64 = 1;
  101. }
  102. base = base | ((u64)base_high << 32);
  103. size = size | ((u64)size_high << 32);
  104. if ((!is_64 && size_low) || (is_64 && size)) {
  105. size = ~size + 1;
  106. printf(" %d %#018llx %#018llx %d %s %s\n",
  107. bar_id, (unsigned long long)base,
  108. (unsigned long long)size, is_64 ? 64 : 32,
  109. is_io ? "I/O" : "MEM",
  110. prefetchable ? "Prefetchable" : "");
  111. }
  112. bar_id++;
  113. bar_cnt--;
  114. }
  115. return 0;
  116. }
  117. static struct pci_reg_info regs_start[] = {
  118. { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
  119. { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
  120. { "command register ID", PCI_SIZE_16, PCI_COMMAND },
  121. { "status register", PCI_SIZE_16, PCI_STATUS },
  122. { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
  123. {},
  124. };
  125. static struct pci_reg_info regs_rest[] = {
  126. { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
  127. { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
  128. { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
  129. { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
  130. { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
  131. { "BIST", PCI_SIZE_8, PCI_BIST },
  132. { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
  133. {},
  134. };
  135. static struct pci_reg_info regs_normal[] = {
  136. { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
  137. { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
  138. { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
  139. { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
  140. { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
  141. { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
  142. { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
  143. { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
  144. { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
  145. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  146. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  147. { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
  148. { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
  149. {},
  150. };
  151. static struct pci_reg_info regs_bridge[] = {
  152. { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
  153. { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
  154. { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
  155. { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
  156. { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
  157. { "IO base", PCI_SIZE_8, PCI_IO_BASE },
  158. { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
  159. { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
  160. { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
  161. { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
  162. { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
  163. { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
  164. { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
  165. { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
  166. { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
  167. { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
  168. { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
  169. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  170. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  171. { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
  172. {},
  173. };
  174. static struct pci_reg_info regs_cardbus[] = {
  175. { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
  176. { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
  177. { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
  178. { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
  179. { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
  180. { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
  181. { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
  182. { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
  183. { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
  184. { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
  185. { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
  186. { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
  187. { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
  188. { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
  189. { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
  190. { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
  191. { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
  192. { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
  193. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  194. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  195. { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
  196. { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
  197. { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
  198. { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
  199. {},
  200. };
  201. /**
  202. * pci_header_show() - Show the header of the specified PCI device.
  203. *
  204. * @dev: Bus+Device+Function number
  205. */
  206. static void pci_header_show(struct udevice *dev)
  207. {
  208. unsigned long class, header_type;
  209. dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
  210. dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
  211. pci_show_regs(dev, regs_start);
  212. printf(" class code = 0x%.2x (%s)\n", (int)class,
  213. pci_class_str(class));
  214. pci_show_regs(dev, regs_rest);
  215. switch (header_type & 0x7f) {
  216. case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
  217. pci_show_regs(dev, regs_normal);
  218. break;
  219. case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
  220. pci_show_regs(dev, regs_bridge);
  221. break;
  222. case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
  223. pci_show_regs(dev, regs_cardbus);
  224. break;
  225. default:
  226. printf("unknown header\n");
  227. break;
  228. }
  229. }
  230. static void pciinfo_header(bool short_listing)
  231. {
  232. if (short_listing) {
  233. printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
  234. printf("_____________________________________________________________\n");
  235. }
  236. }
  237. /**
  238. * pci_header_show_brief() - Show the short-form PCI device header
  239. *
  240. * Reads and prints the header of the specified PCI device in short form.
  241. *
  242. * @dev: PCI device to show
  243. */
  244. static void pci_header_show_brief(struct udevice *dev)
  245. {
  246. ulong vendor, device;
  247. ulong class, subclass;
  248. dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
  249. dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
  250. dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
  251. dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
  252. printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
  253. vendor, device,
  254. pci_class_str(class), subclass);
  255. }
  256. static void pciinfo(struct udevice *bus, bool short_listing, bool multi)
  257. {
  258. struct udevice *dev;
  259. if (!multi)
  260. printf("Scanning PCI devices on bus %d\n", dev_seq(bus));
  261. if (!multi || dev_seq(bus) == 0)
  262. pciinfo_header(short_listing);
  263. for (device_find_first_child(bus, &dev);
  264. dev;
  265. device_find_next_child(&dev)) {
  266. struct pci_child_plat *pplat;
  267. pplat = dev_get_parent_plat(dev);
  268. if (short_listing) {
  269. printf("%02x.%02x.%02x ", dev_seq(bus),
  270. PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
  271. pci_header_show_brief(dev);
  272. } else {
  273. printf("\nFound PCI device %02x.%02x.%02x:\n",
  274. dev_seq(bus),
  275. PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
  276. pci_header_show(dev);
  277. }
  278. }
  279. }
  280. /**
  281. * get_pci_dev() - Convert the "bus.device.function" identifier into a number
  282. *
  283. * @name: Device string in the form "bus.device.function" where each is in hex
  284. * Return: encoded pci_dev_t or -1 if the string was invalid
  285. */
  286. static pci_dev_t get_pci_dev(char *name)
  287. {
  288. char cnum[12];
  289. int len, i, iold, n;
  290. int bdfs[3] = {0,0,0};
  291. len = strlen(name);
  292. if (len > 8)
  293. return -1;
  294. for (i = 0, iold = 0, n = 0; i < len; i++) {
  295. if (name[i] == '.') {
  296. memcpy(cnum, &name[iold], i - iold);
  297. cnum[i - iold] = '\0';
  298. bdfs[n++] = hextoul(cnum, NULL);
  299. iold = i + 1;
  300. }
  301. }
  302. strcpy(cnum, &name[iold]);
  303. if (n == 0)
  304. n = 1;
  305. bdfs[n] = hextoul(cnum, NULL);
  306. return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
  307. }
  308. static int pci_cfg_display(struct udevice *dev, ulong addr,
  309. enum pci_size_t size, ulong length)
  310. {
  311. #define DISP_LINE_LEN 16
  312. ulong i, nbytes, linebytes;
  313. int byte_size;
  314. int rc = 0;
  315. byte_size = pci_byte_size(size);
  316. if (length == 0)
  317. length = 0x40 / byte_size; /* Standard PCI config space */
  318. /* Print the lines.
  319. * once, and all accesses are with the specified bus width.
  320. */
  321. nbytes = length * byte_size;
  322. do {
  323. printf("%08lx:", addr);
  324. linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
  325. for (i = 0; i < linebytes; i += byte_size) {
  326. unsigned long val;
  327. dm_pci_read_config(dev, addr, &val, size);
  328. printf(" %0*lx", pci_field_width(size), val);
  329. addr += byte_size;
  330. }
  331. printf("\n");
  332. nbytes -= linebytes;
  333. if (ctrlc()) {
  334. rc = 1;
  335. break;
  336. }
  337. } while (nbytes > 0);
  338. return (rc);
  339. }
  340. static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
  341. ulong value, int incrflag)
  342. {
  343. ulong i;
  344. int nbytes;
  345. ulong val;
  346. /* Print the address, followed by value. Then accept input for
  347. * the next value. A non-converted value exits.
  348. */
  349. do {
  350. printf("%08lx:", addr);
  351. dm_pci_read_config(dev, addr, &val, size);
  352. printf(" %0*lx", pci_field_width(size), val);
  353. nbytes = cli_readline(" ? ");
  354. if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
  355. /* <CR> pressed as only input, don't modify current
  356. * location and move to next. "-" pressed will go back.
  357. */
  358. if (incrflag)
  359. addr += nbytes ? -size : size;
  360. nbytes = 1;
  361. /* good enough to not time out */
  362. bootretry_reset_cmd_timeout();
  363. }
  364. #ifdef CONFIG_BOOT_RETRY_TIME
  365. else if (nbytes == -2) {
  366. break; /* timed out, exit the command */
  367. }
  368. #endif
  369. else {
  370. char *endp;
  371. i = hextoul(console_buffer, &endp);
  372. nbytes = endp - console_buffer;
  373. if (nbytes) {
  374. /* good enough to not time out
  375. */
  376. bootretry_reset_cmd_timeout();
  377. dm_pci_write_config(dev, addr, i, size);
  378. if (incrflag)
  379. addr += size;
  380. }
  381. }
  382. } while (nbytes);
  383. return 0;
  384. }
  385. static const struct pci_flag_info {
  386. uint flag;
  387. const char *name;
  388. } pci_flag_info[] = {
  389. { PCI_REGION_IO, "io" },
  390. { PCI_REGION_PREFETCH, "prefetch" },
  391. { PCI_REGION_SYS_MEMORY, "sysmem" },
  392. { PCI_REGION_RO, "readonly" },
  393. { PCI_REGION_IO, "io" },
  394. };
  395. static void pci_show_regions(struct udevice *bus)
  396. {
  397. struct pci_controller *hose = dev_get_uclass_priv(pci_get_controller(bus));
  398. const struct pci_region *reg;
  399. int i, j;
  400. if (!hose) {
  401. printf("Bus '%s' is not a PCI controller\n", bus->name);
  402. return;
  403. }
  404. printf("Buses %02x-%02x\n", hose->first_busno, hose->last_busno);
  405. printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
  406. "Flags");
  407. for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
  408. printf("%d %#018llx %#018llx %#018llx ", i,
  409. (unsigned long long)reg->bus_start,
  410. (unsigned long long)reg->phys_start,
  411. (unsigned long long)reg->size);
  412. if (!(reg->flags & PCI_REGION_TYPE))
  413. printf("mem ");
  414. for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
  415. if (reg->flags & pci_flag_info[j].flag)
  416. printf("%s ", pci_flag_info[j].name);
  417. }
  418. printf("\n");
  419. }
  420. }
  421. /* PCI Configuration Space access commands
  422. *
  423. * Syntax:
  424. * pci display[.b, .w, .l] bus.device.function} [addr] [len]
  425. * pci next[.b, .w, .l] bus.device.function [addr]
  426. * pci modify[.b, .w, .l] bus.device.function [addr]
  427. * pci write[.b, .w, .l] bus.device.function addr value
  428. */
  429. static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  430. {
  431. ulong addr = 0, value = 0, cmd_size = 0;
  432. enum pci_size_t size = PCI_SIZE_32;
  433. struct udevice *dev, *bus;
  434. int busnum = -1;
  435. pci_dev_t bdf = 0;
  436. char cmd = 's';
  437. int ret = 0;
  438. char *endp;
  439. if (argc > 1)
  440. cmd = argv[1][0];
  441. switch (cmd) {
  442. case 'd': /* display */
  443. case 'n': /* next */
  444. case 'm': /* modify */
  445. case 'w': /* write */
  446. /* Check for a size specification. */
  447. cmd_size = cmd_get_data_size(argv[1], 4);
  448. size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
  449. if (argc > 3)
  450. addr = hextoul(argv[3], NULL);
  451. if (argc > 4)
  452. value = hextoul(argv[4], NULL);
  453. case 'h': /* header */
  454. case 'b': /* bars */
  455. if (argc < 3)
  456. goto usage;
  457. if ((bdf = get_pci_dev(argv[2])) == -1)
  458. return 1;
  459. break;
  460. case 'e':
  461. pci_init();
  462. return 0;
  463. case 'r': /* no break */
  464. default: /* scan bus */
  465. value = 1; /* short listing */
  466. if (argc > 1) {
  467. if (cmd != 'r' && argv[argc-1][0] == 'l') {
  468. value = 0;
  469. argc--;
  470. }
  471. if (argc > 2 || (argc > 1 && cmd != 'r' && argv[1][0] != 's')) {
  472. if (argv[argc - 1][0] != '*') {
  473. busnum = hextoul(argv[argc - 1], &endp);
  474. if (*endp)
  475. goto usage;
  476. }
  477. argc--;
  478. }
  479. if (cmd == 'r' && argc > 2)
  480. goto usage;
  481. else if (cmd != 'r' && (argc > 2 || (argc == 2 && argv[1][0] != 's')))
  482. goto usage;
  483. }
  484. if (busnum == -1) {
  485. if (cmd != 'r') {
  486. for (busnum = 0;
  487. uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
  488. busnum++)
  489. pciinfo(bus, value, true);
  490. } else {
  491. for (busnum = 0;
  492. uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
  493. busnum++) {
  494. /* Regions are controller specific so skip non-root buses */
  495. if (device_is_on_pci_bus(bus))
  496. continue;
  497. pci_show_regions(bus);
  498. }
  499. }
  500. return 0;
  501. }
  502. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
  503. if (ret) {
  504. printf("No such bus\n");
  505. return CMD_RET_FAILURE;
  506. }
  507. if (cmd == 'r')
  508. pci_show_regions(bus);
  509. else
  510. pciinfo(bus, value, false);
  511. return 0;
  512. }
  513. ret = dm_pci_bus_find_bdf(bdf, &dev);
  514. if (ret) {
  515. printf("No such device\n");
  516. return CMD_RET_FAILURE;
  517. }
  518. switch (argv[1][0]) {
  519. case 'h': /* header */
  520. pci_header_show(dev);
  521. break;
  522. case 'd': /* display */
  523. return pci_cfg_display(dev, addr, size, value);
  524. case 'n': /* next */
  525. if (argc < 4)
  526. goto usage;
  527. ret = pci_cfg_modify(dev, addr, size, value, 0);
  528. break;
  529. case 'm': /* modify */
  530. if (argc < 4)
  531. goto usage;
  532. ret = pci_cfg_modify(dev, addr, size, value, 1);
  533. break;
  534. case 'w': /* write */
  535. if (argc < 5)
  536. goto usage;
  537. ret = dm_pci_write_config(dev, addr, value, size);
  538. break;
  539. case 'b': /* bars */
  540. return pci_bar_show(dev);
  541. default:
  542. ret = CMD_RET_USAGE;
  543. break;
  544. }
  545. return ret;
  546. usage:
  547. return CMD_RET_USAGE;
  548. }
  549. /***************************************************/
  550. #ifdef CONFIG_SYS_LONGHELP
  551. static char pci_help_text[] =
  552. "[bus|*] [long]\n"
  553. " - short or long list of PCI devices on bus 'bus'\n"
  554. "pci enum\n"
  555. " - Enumerate PCI buses\n"
  556. "pci header b.d.f\n"
  557. " - show header of PCI device 'bus.device.function'\n"
  558. "pci bar b.d.f\n"
  559. " - show BARs base and size for device b.d.f'\n"
  560. "pci regions [bus|*]\n"
  561. " - show PCI regions\n"
  562. "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
  563. " - display PCI configuration space (CFG)\n"
  564. "pci next[.b, .w, .l] b.d.f address\n"
  565. " - modify, read and keep CFG address\n"
  566. "pci modify[.b, .w, .l] b.d.f address\n"
  567. " - modify, auto increment CFG address\n"
  568. "pci write[.b, .w, .l] b.d.f address value\n"
  569. " - write to CFG address";
  570. #endif
  571. U_BOOT_CMD(
  572. pci, 5, 1, do_pci,
  573. "list and access PCI Configuration Space", pci_help_text
  574. );