pci.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Andreas Heppel <aheppel@sysgo.de>
  5. *
  6. * (C) Copyright 2002
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
  9. */
  10. /*
  11. * PCI routines
  12. */
  13. #include <common.h>
  14. #include <bootretry.h>
  15. #include <cli.h>
  16. #include <command.h>
  17. #include <console.h>
  18. #include <dm.h>
  19. #include <init.h>
  20. #include <asm/processor.h>
  21. #include <asm/io.h>
  22. #include <pci.h>
  23. struct pci_reg_info {
  24. const char *name;
  25. enum pci_size_t size;
  26. u8 offset;
  27. };
  28. static int pci_byte_size(enum pci_size_t size)
  29. {
  30. switch (size) {
  31. case PCI_SIZE_8:
  32. return 1;
  33. case PCI_SIZE_16:
  34. return 2;
  35. case PCI_SIZE_32:
  36. default:
  37. return 4;
  38. }
  39. }
  40. static int pci_field_width(enum pci_size_t size)
  41. {
  42. return pci_byte_size(size) * 2;
  43. }
  44. static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
  45. {
  46. for (; regs->name; regs++) {
  47. unsigned long val;
  48. dm_pci_read_config(dev, regs->offset, &val, regs->size);
  49. printf(" %s =%*s%#.*lx\n", regs->name,
  50. (int)(28 - strlen(regs->name)), "",
  51. pci_field_width(regs->size), val);
  52. }
  53. }
  54. static int pci_bar_show(struct udevice *dev)
  55. {
  56. u8 header_type;
  57. int bar_cnt, bar_id, mem_type;
  58. bool is_64, is_io;
  59. u32 base_low, base_high;
  60. u32 size_low, size_high;
  61. u64 base, size;
  62. u32 reg_addr;
  63. int prefetchable;
  64. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  65. header_type &= 0x7f;
  66. if (header_type == PCI_HEADER_TYPE_CARDBUS) {
  67. printf("CardBus doesn't support BARs\n");
  68. return -ENOSYS;
  69. } else if (header_type != PCI_HEADER_TYPE_NORMAL &&
  70. header_type != PCI_HEADER_TYPE_BRIDGE) {
  71. printf("unknown header type\n");
  72. return -ENOSYS;
  73. }
  74. bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
  75. printf("ID Base Size Width Type\n");
  76. printf("----------------------------------------------------------\n");
  77. bar_id = 0;
  78. reg_addr = PCI_BASE_ADDRESS_0;
  79. while (bar_cnt) {
  80. dm_pci_read_config32(dev, reg_addr, &base_low);
  81. dm_pci_write_config32(dev, reg_addr, 0xffffffff);
  82. dm_pci_read_config32(dev, reg_addr, &size_low);
  83. dm_pci_write_config32(dev, reg_addr, base_low);
  84. reg_addr += 4;
  85. base = base_low & ~0xf;
  86. size = size_low & ~0xf;
  87. base_high = 0x0;
  88. size_high = 0xffffffff;
  89. is_64 = 0;
  90. prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
  91. is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
  92. mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  93. if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
  94. dm_pci_read_config32(dev, reg_addr, &base_high);
  95. dm_pci_write_config32(dev, reg_addr, 0xffffffff);
  96. dm_pci_read_config32(dev, reg_addr, &size_high);
  97. dm_pci_write_config32(dev, reg_addr, base_high);
  98. bar_cnt--;
  99. reg_addr += 4;
  100. is_64 = 1;
  101. }
  102. base = base | ((u64)base_high << 32);
  103. size = size | ((u64)size_high << 32);
  104. if ((!is_64 && size_low) || (is_64 && size)) {
  105. size = ~size + 1;
  106. printf(" %d %#018llx %#018llx %d %s %s\n",
  107. bar_id, (unsigned long long)base,
  108. (unsigned long long)size, is_64 ? 64 : 32,
  109. is_io ? "I/O" : "MEM",
  110. prefetchable ? "Prefetchable" : "");
  111. }
  112. bar_id++;
  113. bar_cnt--;
  114. }
  115. return 0;
  116. }
  117. static struct pci_reg_info regs_start[] = {
  118. { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
  119. { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
  120. { "command register ID", PCI_SIZE_16, PCI_COMMAND },
  121. { "status register", PCI_SIZE_16, PCI_STATUS },
  122. { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
  123. {},
  124. };
  125. static struct pci_reg_info regs_rest[] = {
  126. { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
  127. { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
  128. { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
  129. { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
  130. { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
  131. { "BIST", PCI_SIZE_8, PCI_BIST },
  132. { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
  133. {},
  134. };
  135. static struct pci_reg_info regs_normal[] = {
  136. { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
  137. { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
  138. { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
  139. { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
  140. { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
  141. { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
  142. { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
  143. { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
  144. { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
  145. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  146. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  147. { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
  148. { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
  149. {},
  150. };
  151. static struct pci_reg_info regs_bridge[] = {
  152. { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
  153. { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
  154. { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
  155. { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
  156. { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
  157. { "IO base", PCI_SIZE_8, PCI_IO_BASE },
  158. { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
  159. { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
  160. { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
  161. { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
  162. { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
  163. { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
  164. { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
  165. { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
  166. { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
  167. { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
  168. { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
  169. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  170. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  171. { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
  172. {},
  173. };
  174. static struct pci_reg_info regs_cardbus[] = {
  175. { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
  176. { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
  177. { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
  178. { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
  179. { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
  180. { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
  181. { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
  182. { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
  183. { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
  184. { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
  185. { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
  186. { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
  187. { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
  188. { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
  189. { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
  190. { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
  191. { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
  192. { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
  193. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  194. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  195. { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
  196. { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
  197. { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
  198. { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
  199. {},
  200. };
  201. /**
  202. * pci_header_show() - Show the header of the specified PCI device.
  203. *
  204. * @dev: Bus+Device+Function number
  205. */
  206. static void pci_header_show(struct udevice *dev)
  207. {
  208. unsigned long class, header_type;
  209. dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
  210. dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
  211. pci_show_regs(dev, regs_start);
  212. printf(" class code = 0x%.2x (%s)\n", (int)class,
  213. pci_class_str(class));
  214. pci_show_regs(dev, regs_rest);
  215. switch (header_type & 0x7f) {
  216. case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
  217. pci_show_regs(dev, regs_normal);
  218. break;
  219. case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
  220. pci_show_regs(dev, regs_bridge);
  221. break;
  222. case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
  223. pci_show_regs(dev, regs_cardbus);
  224. break;
  225. default:
  226. printf("unknown header\n");
  227. break;
  228. }
  229. }
  230. static void pciinfo_header(int busnum, bool short_listing)
  231. {
  232. printf("Scanning PCI devices on bus %d\n", busnum);
  233. if (short_listing) {
  234. printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
  235. printf("_____________________________________________________________\n");
  236. }
  237. }
  238. /**
  239. * pci_header_show_brief() - Show the short-form PCI device header
  240. *
  241. * Reads and prints the header of the specified PCI device in short form.
  242. *
  243. * @dev: PCI device to show
  244. */
  245. static void pci_header_show_brief(struct udevice *dev)
  246. {
  247. ulong vendor, device;
  248. ulong class, subclass;
  249. dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
  250. dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
  251. dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
  252. dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
  253. printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
  254. vendor, device,
  255. pci_class_str(class), subclass);
  256. }
  257. static void pciinfo(struct udevice *bus, bool short_listing)
  258. {
  259. struct udevice *dev;
  260. pciinfo_header(dev_seq(bus), short_listing);
  261. for (device_find_first_child(bus, &dev);
  262. dev;
  263. device_find_next_child(&dev)) {
  264. struct pci_child_plat *pplat;
  265. pplat = dev_get_parent_plat(dev);
  266. if (short_listing) {
  267. printf("%02x.%02x.%02x ", dev_seq(bus),
  268. PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
  269. pci_header_show_brief(dev);
  270. } else {
  271. printf("\nFound PCI device %02x.%02x.%02x:\n",
  272. dev_seq(bus),
  273. PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
  274. pci_header_show(dev);
  275. }
  276. }
  277. }
  278. /**
  279. * get_pci_dev() - Convert the "bus.device.function" identifier into a number
  280. *
  281. * @name: Device string in the form "bus.device.function" where each is in hex
  282. * @return encoded pci_dev_t or -1 if the string was invalid
  283. */
  284. static pci_dev_t get_pci_dev(char *name)
  285. {
  286. char cnum[12];
  287. int len, i, iold, n;
  288. int bdfs[3] = {0,0,0};
  289. len = strlen(name);
  290. if (len > 8)
  291. return -1;
  292. for (i = 0, iold = 0, n = 0; i < len; i++) {
  293. if (name[i] == '.') {
  294. memcpy(cnum, &name[iold], i - iold);
  295. cnum[i - iold] = '\0';
  296. bdfs[n++] = hextoul(cnum, NULL);
  297. iold = i + 1;
  298. }
  299. }
  300. strcpy(cnum, &name[iold]);
  301. if (n == 0)
  302. n = 1;
  303. bdfs[n] = hextoul(cnum, NULL);
  304. return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
  305. }
  306. static int pci_cfg_display(struct udevice *dev, ulong addr,
  307. enum pci_size_t size, ulong length)
  308. {
  309. #define DISP_LINE_LEN 16
  310. ulong i, nbytes, linebytes;
  311. int byte_size;
  312. int rc = 0;
  313. byte_size = pci_byte_size(size);
  314. if (length == 0)
  315. length = 0x40 / byte_size; /* Standard PCI config space */
  316. /* Print the lines.
  317. * once, and all accesses are with the specified bus width.
  318. */
  319. nbytes = length * byte_size;
  320. do {
  321. printf("%08lx:", addr);
  322. linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
  323. for (i = 0; i < linebytes; i += byte_size) {
  324. unsigned long val;
  325. dm_pci_read_config(dev, addr, &val, size);
  326. printf(" %0*lx", pci_field_width(size), val);
  327. addr += byte_size;
  328. }
  329. printf("\n");
  330. nbytes -= linebytes;
  331. if (ctrlc()) {
  332. rc = 1;
  333. break;
  334. }
  335. } while (nbytes > 0);
  336. return (rc);
  337. }
  338. static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
  339. ulong value, int incrflag)
  340. {
  341. ulong i;
  342. int nbytes;
  343. ulong val;
  344. /* Print the address, followed by value. Then accept input for
  345. * the next value. A non-converted value exits.
  346. */
  347. do {
  348. printf("%08lx:", addr);
  349. dm_pci_read_config(dev, addr, &val, size);
  350. printf(" %0*lx", pci_field_width(size), val);
  351. nbytes = cli_readline(" ? ");
  352. if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
  353. /* <CR> pressed as only input, don't modify current
  354. * location and move to next. "-" pressed will go back.
  355. */
  356. if (incrflag)
  357. addr += nbytes ? -size : size;
  358. nbytes = 1;
  359. /* good enough to not time out */
  360. bootretry_reset_cmd_timeout();
  361. }
  362. #ifdef CONFIG_BOOT_RETRY_TIME
  363. else if (nbytes == -2) {
  364. break; /* timed out, exit the command */
  365. }
  366. #endif
  367. else {
  368. char *endp;
  369. i = hextoul(console_buffer, &endp);
  370. nbytes = endp - console_buffer;
  371. if (nbytes) {
  372. /* good enough to not time out
  373. */
  374. bootretry_reset_cmd_timeout();
  375. dm_pci_write_config(dev, addr, i, size);
  376. if (incrflag)
  377. addr += size;
  378. }
  379. }
  380. } while (nbytes);
  381. return 0;
  382. }
  383. static const struct pci_flag_info {
  384. uint flag;
  385. const char *name;
  386. } pci_flag_info[] = {
  387. { PCI_REGION_IO, "io" },
  388. { PCI_REGION_PREFETCH, "prefetch" },
  389. { PCI_REGION_SYS_MEMORY, "sysmem" },
  390. { PCI_REGION_RO, "readonly" },
  391. { PCI_REGION_IO, "io" },
  392. };
  393. static void pci_show_regions(struct udevice *bus)
  394. {
  395. struct pci_controller *hose = dev_get_uclass_priv(bus);
  396. const struct pci_region *reg;
  397. int i, j;
  398. if (!hose) {
  399. printf("Bus '%s' is not a PCI controller\n", bus->name);
  400. return;
  401. }
  402. printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
  403. "Flags");
  404. for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
  405. printf("%d %#018llx %#018llx %#018llx ", i,
  406. (unsigned long long)reg->bus_start,
  407. (unsigned long long)reg->phys_start,
  408. (unsigned long long)reg->size);
  409. if (!(reg->flags & PCI_REGION_TYPE))
  410. printf("mem ");
  411. for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
  412. if (reg->flags & pci_flag_info[j].flag)
  413. printf("%s ", pci_flag_info[j].name);
  414. }
  415. printf("\n");
  416. }
  417. }
  418. /* PCI Configuration Space access commands
  419. *
  420. * Syntax:
  421. * pci display[.b, .w, .l] bus.device.function} [addr] [len]
  422. * pci next[.b, .w, .l] bus.device.function [addr]
  423. * pci modify[.b, .w, .l] bus.device.function [addr]
  424. * pci write[.b, .w, .l] bus.device.function addr value
  425. */
  426. static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  427. {
  428. ulong addr = 0, value = 0, cmd_size = 0;
  429. enum pci_size_t size = PCI_SIZE_32;
  430. struct udevice *dev, *bus;
  431. int busnum = 0;
  432. pci_dev_t bdf = 0;
  433. char cmd = 's';
  434. int ret = 0;
  435. if (argc > 1)
  436. cmd = argv[1][0];
  437. switch (cmd) {
  438. case 'd': /* display */
  439. case 'n': /* next */
  440. case 'm': /* modify */
  441. case 'w': /* write */
  442. /* Check for a size specification. */
  443. cmd_size = cmd_get_data_size(argv[1], 4);
  444. size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
  445. if (argc > 3)
  446. addr = hextoul(argv[3], NULL);
  447. if (argc > 4)
  448. value = hextoul(argv[4], NULL);
  449. case 'h': /* header */
  450. case 'b': /* bars */
  451. if (argc < 3)
  452. goto usage;
  453. if ((bdf = get_pci_dev(argv[2])) == -1)
  454. return 1;
  455. break;
  456. case 'e':
  457. pci_init();
  458. return 0;
  459. case 'r': /* no break */
  460. default: /* scan bus */
  461. value = 1; /* short listing */
  462. if (argc > 1) {
  463. if (cmd != 'r' && argv[argc-1][0] == 'l') {
  464. value = 0;
  465. argc--;
  466. }
  467. if (argc > 1)
  468. busnum = hextoul(argv[1], NULL);
  469. }
  470. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
  471. if (ret) {
  472. printf("No such bus\n");
  473. return CMD_RET_FAILURE;
  474. }
  475. if (cmd == 'r')
  476. pci_show_regions(bus);
  477. else
  478. pciinfo(bus, value);
  479. return 0;
  480. }
  481. ret = dm_pci_bus_find_bdf(bdf, &dev);
  482. if (ret) {
  483. printf("No such device\n");
  484. return CMD_RET_FAILURE;
  485. }
  486. switch (argv[1][0]) {
  487. case 'h': /* header */
  488. pci_header_show(dev);
  489. break;
  490. case 'd': /* display */
  491. return pci_cfg_display(dev, addr, size, value);
  492. case 'n': /* next */
  493. if (argc < 4)
  494. goto usage;
  495. ret = pci_cfg_modify(dev, addr, size, value, 0);
  496. break;
  497. case 'm': /* modify */
  498. if (argc < 4)
  499. goto usage;
  500. ret = pci_cfg_modify(dev, addr, size, value, 1);
  501. break;
  502. case 'w': /* write */
  503. if (argc < 5)
  504. goto usage;
  505. ret = dm_pci_write_config(dev, addr, value, size);
  506. break;
  507. case 'b': /* bars */
  508. return pci_bar_show(dev);
  509. default:
  510. ret = CMD_RET_USAGE;
  511. break;
  512. }
  513. return ret;
  514. usage:
  515. return CMD_RET_USAGE;
  516. }
  517. /***************************************************/
  518. #ifdef CONFIG_SYS_LONGHELP
  519. static char pci_help_text[] =
  520. "[bus] [long]\n"
  521. " - short or long list of PCI devices on bus 'bus'\n"
  522. "pci enum\n"
  523. " - Enumerate PCI buses\n"
  524. "pci header b.d.f\n"
  525. " - show header of PCI device 'bus.device.function'\n"
  526. "pci bar b.d.f\n"
  527. " - show BARs base and size for device b.d.f'\n"
  528. "pci regions\n"
  529. " - show PCI regions\n"
  530. "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
  531. " - display PCI configuration space (CFG)\n"
  532. "pci next[.b, .w, .l] b.d.f address\n"
  533. " - modify, read and keep CFG address\n"
  534. "pci modify[.b, .w, .l] b.d.f address\n"
  535. " - modify, auto increment CFG address\n"
  536. "pci write[.b, .w, .l] b.d.f address value\n"
  537. " - write to CFG address";
  538. #endif
  539. U_BOOT_CMD(
  540. pci, 5, 1, do_pci,
  541. "list and access PCI Configuration Space", pci_help_text
  542. );