mpc83xx.h 48 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __MPC83XX_H__
  6. #define __MPC83XX_H__
  7. #include <config.h>
  8. #include <asm/fsl_lbc.h>
  9. #if defined(CONFIG_E300)
  10. #include <asm/e300.h>
  11. #endif
  12. /*
  13. * System reset offset (PowerPC standard)
  14. */
  15. #define EXC_OFF_SYS_RESET 0x0100
  16. #define _START_OFFSET EXC_OFF_SYS_RESET
  17. /*
  18. * IMMRBAR - Internal Memory Register Base Address
  19. */
  20. #ifndef CONFIG_DEFAULT_IMMR
  21. /* Default IMMR base address */
  22. #define CONFIG_DEFAULT_IMMR 0xFF400000
  23. #endif
  24. /* Register offset to immr */
  25. #define IMMRBAR 0x0000
  26. #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
  27. #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
  28. /*
  29. * LAWBAR - Local Access Window Base Address Register
  30. */
  31. /* Register offset to immr */
  32. #define LBLAWBAR0 0x0020
  33. #define LBLAWAR0 0x0024
  34. #define LBLAWBAR1 0x0028
  35. #define LBLAWAR1 0x002C
  36. #define LBLAWBAR2 0x0030
  37. #define LBLAWAR2 0x0034
  38. #define LBLAWBAR3 0x0038
  39. #define LBLAWAR3 0x003C
  40. #define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */
  41. /*
  42. * SPRIDR - System Part and Revision ID Register
  43. */
  44. #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
  45. #define SPRIDR_REVID 0x0000FFFF /* Revision Id */
  46. #if defined(CONFIG_ARCH_MPC834X)
  47. #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
  48. #define REVID_MINOR(spridr) (spridr & 0x000000FF)
  49. #else
  50. #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
  51. #define REVID_MINOR(spridr) (spridr & 0x0000000F)
  52. #endif
  53. #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
  54. #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
  55. #define SPR_8308 0x8100
  56. #define SPR_8309 0x8110
  57. #define SPR_831X_FAMILY 0x80B
  58. #define SPR_8311 0x80B2
  59. #define SPR_8313 0x80B0
  60. #define SPR_8314 0x80B6
  61. #define SPR_8315 0x80B4
  62. #define SPR_832X_FAMILY 0x806
  63. #define SPR_8321 0x8066
  64. #define SPR_8323 0x8062
  65. #define SPR_834X_FAMILY 0x803
  66. #define SPR_8343 0x8036
  67. #define SPR_8347_TBGA_ 0x8032
  68. #define SPR_8347_PBGA_ 0x8034
  69. #define SPR_8349 0x8030
  70. #define SPR_836X_FAMILY 0x804
  71. #define SPR_8358_TBGA_ 0x804A
  72. #define SPR_8358_PBGA_ 0x804E
  73. #define SPR_8360 0x8048
  74. #define SPR_837X_FAMILY 0x80C
  75. #define SPR_8377 0x80C6
  76. #define SPR_8378 0x80C4
  77. #define SPR_8379 0x80C2
  78. /*
  79. * SPCR - System Priority Configuration Register
  80. */
  81. /* PCI Highest Priority Enable */
  82. #define SPCR_PCIHPE 0x10000000
  83. #define SPCR_PCIHPE_SHIFT (31-3)
  84. /* PCI bridge system bus request priority */
  85. #define SPCR_PCIPR 0x03000000
  86. #define SPCR_PCIPR_SHIFT (31-7)
  87. #define SPCR_OPT 0x00800000 /* Optimize */
  88. #define SPCR_OPT_SHIFT (31-8)
  89. /* E300 PowerPC core time base unit enable */
  90. #define SPCR_TBEN 0x00400000
  91. #define SPCR_TBEN_SHIFT (31-9)
  92. /* E300 PowerPC Core system bus request priority */
  93. #define SPCR_COREPR 0x00300000
  94. #define SPCR_COREPR_SHIFT (31-11)
  95. #if defined(CONFIG_ARCH_MPC834X)
  96. /* SPCR bits - MPC8349 specific */
  97. /* TSEC1 data priority */
  98. #define SPCR_TSEC1DP 0x00003000
  99. #define SPCR_TSEC1DP_SHIFT (31-19)
  100. /* TSEC1 buffer descriptor priority */
  101. #define SPCR_TSEC1BDP 0x00000C00
  102. #define SPCR_TSEC1BDP_SHIFT (31-21)
  103. /* TSEC1 emergency priority */
  104. #define SPCR_TSEC1EP 0x00000300
  105. #define SPCR_TSEC1EP_SHIFT (31-23)
  106. /* TSEC2 data priority */
  107. #define SPCR_TSEC2DP 0x00000030
  108. #define SPCR_TSEC2DP_SHIFT (31-27)
  109. /* TSEC2 buffer descriptor priority */
  110. #define SPCR_TSEC2BDP 0x0000000C
  111. #define SPCR_TSEC2BDP_SHIFT (31-29)
  112. /* TSEC2 emergency priority */
  113. #define SPCR_TSEC2EP 0x00000003
  114. #define SPCR_TSEC2EP_SHIFT (31-31)
  115. #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  116. defined(CONFIG_ARCH_MPC837X)
  117. /* SPCR bits - MPC8308, MPC831x and MPC837X specific */
  118. /* TSEC data priority */
  119. #define SPCR_TSECDP 0x00003000
  120. #define SPCR_TSECDP_SHIFT (31-19)
  121. /* TSEC buffer descriptor priority */
  122. #define SPCR_TSECBDP 0x00000C00
  123. #define SPCR_TSECBDP_SHIFT (31-21)
  124. /* TSEC emergency priority */
  125. #define SPCR_TSECEP 0x00000300
  126. #define SPCR_TSECEP_SHIFT (31-23)
  127. #endif
  128. /* SICRL/H - System I/O Configuration Register Low/High
  129. */
  130. #if defined(CONFIG_ARCH_MPC834X)
  131. /* SICRL bits - MPC8349 specific */
  132. #define SICRL_LDP_A 0x80000000
  133. #define SICRL_USB1 0x40000000
  134. #define SICRL_USB0 0x20000000
  135. #define SICRL_UART 0x0C000000
  136. #define SICRL_GPIO1_A 0x02000000
  137. #define SICRL_GPIO1_B 0x01000000
  138. #define SICRL_GPIO1_C 0x00800000
  139. #define SICRL_GPIO1_D 0x00400000
  140. #define SICRL_GPIO1_E 0x00200000
  141. #define SICRL_GPIO1_F 0x00180000
  142. #define SICRL_GPIO1_G 0x00040000
  143. #define SICRL_GPIO1_H 0x00020000
  144. #define SICRL_GPIO1_I 0x00010000
  145. #define SICRL_GPIO1_J 0x00008000
  146. #define SICRL_GPIO1_K 0x00004000
  147. #define SICRL_GPIO1_L 0x00003000
  148. /* SICRH bits - MPC8349 specific */
  149. #define SICRH_DDR 0x80000000
  150. #define SICRH_TSEC1_A 0x10000000
  151. #define SICRH_TSEC1_B 0x08000000
  152. #define SICRH_TSEC1_C 0x04000000
  153. #define SICRH_TSEC1_D 0x02000000
  154. #define SICRH_TSEC1_E 0x01000000
  155. #define SICRH_TSEC1_F 0x00800000
  156. #define SICRH_TSEC2_A 0x00400000
  157. #define SICRH_TSEC2_B 0x00200000
  158. #define SICRH_TSEC2_C 0x00100000
  159. #define SICRH_TSEC2_D 0x00080000
  160. #define SICRH_TSEC2_E 0x00040000
  161. #define SICRH_TSEC2_F 0x00020000
  162. #define SICRH_TSEC2_G 0x00010000
  163. #define SICRH_TSEC2_H 0x00008000
  164. #define SICRH_GPIO2_A 0x00004000
  165. #define SICRH_GPIO2_B 0x00002000
  166. #define SICRH_GPIO2_C 0x00001000
  167. #define SICRH_GPIO2_D 0x00000800
  168. #define SICRH_GPIO2_E 0x00000400
  169. #define SICRH_GPIO2_F 0x00000200
  170. #define SICRH_GPIO2_G 0x00000180
  171. #define SICRH_GPIO2_H 0x00000060
  172. #define SICRH_TSOBI1 0x00000002
  173. #define SICRH_TSOBI2 0x00000001
  174. #elif defined(CONFIG_ARCH_MPC8360)
  175. /* SICRL bits - MPC8360 specific */
  176. #define SICRL_LDP_A 0xC0000000
  177. #define SICRL_LCLK_1 0x10000000
  178. #define SICRL_LCLK_2 0x08000000
  179. #define SICRL_SRCID_A 0x03000000
  180. #define SICRL_IRQ_CKSTP_A 0x00C00000
  181. /* SICRH bits - MPC8360 specific */
  182. #define SICRH_DDR 0x80000000
  183. #define SICRH_SECONDARY_DDR 0x40000000
  184. #define SICRH_SDDROE 0x20000000
  185. #define SICRH_IRQ3 0x10000000
  186. #define SICRH_UC1EOBI 0x00000004
  187. #define SICRH_UC2E1OBI 0x00000002
  188. #define SICRH_UC2E2OBI 0x00000001
  189. #elif defined(CONFIG_ARCH_MPC832X)
  190. /* SICRL bits - MPC832x specific */
  191. #define SICRL_LDP_LCS_A 0x80000000
  192. #define SICRL_IRQ_CKS 0x20000000
  193. #define SICRL_PCI_MSRC 0x10000000
  194. #define SICRL_URT_CTPR 0x06000000
  195. #define SICRL_IRQ_CTPR 0x00C00000
  196. #elif defined(CONFIG_ARCH_MPC8313)
  197. /* SICRL bits - MPC8313 specific */
  198. #define SICRL_LBC 0x30000000
  199. #define SICRL_UART 0x0C000000
  200. #define SICRL_SPI_A 0x03000000
  201. #define SICRL_SPI_B 0x00C00000
  202. #define SICRL_SPI_C 0x00300000
  203. #define SICRL_SPI_D 0x000C0000
  204. #define SICRL_USBDR_11 0x00000C00
  205. #define SICRL_USBDR_10 0x00000800
  206. #define SICRL_USBDR_01 0x00000400
  207. #define SICRL_USBDR_00 0x00000000
  208. #define SICRL_ETSEC1_A 0x0000000C
  209. #define SICRL_ETSEC2_A 0x00000003
  210. /* SICRH bits - MPC8313 specific */
  211. #define SICRH_INTR_A 0x02000000
  212. #define SICRH_INTR_B 0x00C00000
  213. #define SICRH_IIC 0x00300000
  214. #define SICRH_ETSEC2_B 0x000C0000
  215. #define SICRH_ETSEC2_C 0x00030000
  216. #define SICRH_ETSEC2_D 0x0000C000
  217. #define SICRH_ETSEC2_E 0x00003000
  218. #define SICRH_ETSEC2_F 0x00000C00
  219. #define SICRH_ETSEC2_G 0x00000300
  220. #define SICRH_ETSEC1_B 0x00000080
  221. #define SICRH_ETSEC1_C 0x00000060
  222. #define SICRH_GTX1_DLY 0x00000008
  223. #define SICRH_GTX2_DLY 0x00000004
  224. #define SICRH_TSOBI1 0x00000002
  225. #define SICRH_TSOBI2 0x00000001
  226. #elif defined(CONFIG_ARCH_MPC837X)
  227. /* SICRL bits - MPC837X specific */
  228. #define SICRL_USB_A 0xC0000000
  229. #define SICRL_USB_B 0x30000000
  230. #define SICRL_USB_B_SD 0x20000000
  231. #define SICRL_UART 0x0C000000
  232. #define SICRL_GPIO_A 0x02000000
  233. #define SICRL_GPIO_B 0x01000000
  234. #define SICRL_GPIO_C 0x00800000
  235. #define SICRL_GPIO_D 0x00400000
  236. #define SICRL_GPIO_E 0x00200000
  237. #define SICRL_GPIO_F 0x00180000
  238. #define SICRL_GPIO_G 0x00040000
  239. #define SICRL_GPIO_H 0x00020000
  240. #define SICRL_GPIO_I 0x00010000
  241. #define SICRL_GPIO_J 0x00008000
  242. #define SICRL_GPIO_K 0x00004000
  243. #define SICRL_GPIO_L 0x00003000
  244. #define SICRL_DMA_A 0x00000800
  245. #define SICRL_DMA_B 0x00000400
  246. #define SICRL_DMA_C 0x00000200
  247. #define SICRL_DMA_D 0x00000100
  248. #define SICRL_DMA_E 0x00000080
  249. #define SICRL_DMA_F 0x00000040
  250. #define SICRL_DMA_G 0x00000020
  251. #define SICRL_DMA_H 0x00000010
  252. #define SICRL_DMA_I 0x00000008
  253. #define SICRL_DMA_J 0x00000004
  254. #define SICRL_LDP_A 0x00000002
  255. #define SICRL_LDP_B 0x00000001
  256. /* SICRH bits - MPC837X specific */
  257. #define SICRH_DDR 0x80000000
  258. #define SICRH_TSEC1_A 0x10000000
  259. #define SICRH_TSEC1_B 0x08000000
  260. #define SICRH_TSEC2_A 0x00400000
  261. #define SICRH_TSEC2_B 0x00200000
  262. #define SICRH_TSEC2_C 0x00100000
  263. #define SICRH_TSEC2_D 0x00080000
  264. #define SICRH_TSEC2_E 0x00040000
  265. #define SICRH_TMR 0x00010000
  266. #define SICRH_GPIO2_A 0x00008000
  267. #define SICRH_GPIO2_B 0x00004000
  268. #define SICRH_GPIO2_C 0x00002000
  269. #define SICRH_GPIO2_D 0x00001000
  270. #define SICRH_GPIO2_E 0x00000C00
  271. #define SICRH_GPIO2_E_SD 0x00000800
  272. #define SICRH_GPIO2_F 0x00000300
  273. #define SICRH_GPIO2_G 0x000000C0
  274. #define SICRH_GPIO2_H 0x00000030
  275. #define SICRH_SPI 0x00000003
  276. #define SICRH_SPI_SD 0x00000001
  277. #elif defined(CONFIG_ARCH_MPC8308)
  278. /* SICRL bits - MPC8308 specific */
  279. #define SICRL_SPI_PF0 (0 << 28)
  280. #define SICRL_SPI_PF1 (1 << 28)
  281. #define SICRL_SPI_PF3 (3 << 28)
  282. #define SICRL_UART_PF0 (0 << 26)
  283. #define SICRL_UART_PF1 (1 << 26)
  284. #define SICRL_UART_PF3 (3 << 26)
  285. #define SICRL_IRQ_PF0 (0 << 24)
  286. #define SICRL_IRQ_PF1 (1 << 24)
  287. #define SICRL_I2C2_PF0 (0 << 20)
  288. #define SICRL_I2C2_PF1 (1 << 20)
  289. #define SICRL_ETSEC1_TX_CLK (0 << 6)
  290. #define SICRL_ETSEC1_GTX_CLK125 (1 << 6)
  291. /* SICRH bits - MPC8308 specific */
  292. #define SICRH_ESDHC_A_SD (0 << 30)
  293. #define SICRH_ESDHC_A_GTM (1 << 30)
  294. #define SICRH_ESDHC_A_GPIO (3 << 30)
  295. #define SICRH_ESDHC_B_SD (0 << 28)
  296. #define SICRH_ESDHC_B_GTM (1 << 28)
  297. #define SICRH_ESDHC_B_GPIO (3 << 28)
  298. #define SICRH_ESDHC_C_SD (0 << 26)
  299. #define SICRH_ESDHC_C_GTM (1 << 26)
  300. #define SICRH_ESDHC_C_GPIO (3 << 26)
  301. #define SICRH_GPIO_A_GPIO (0 << 24)
  302. #define SICRH_GPIO_A_TSEC2 (1 << 24)
  303. #define SICRH_GPIO_B_GPIO (0 << 22)
  304. #define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22)
  305. #define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22)
  306. #define SICRH_IEEE1588_A_TMR (1 << 20)
  307. #define SICRH_IEEE1588_A_GPIO (3 << 20)
  308. #define SICRH_USB (1 << 18)
  309. #define SICRH_GTM_GTM (1 << 16)
  310. #define SICRH_GTM_GPIO (3 << 16)
  311. #define SICRH_IEEE1588_B_TMR (1 << 14)
  312. #define SICRH_IEEE1588_B_GPIO (3 << 14)
  313. #define SICRH_ETSEC2_CRS (1 << 12)
  314. #define SICRH_ETSEC2_GPIO (3 << 12)
  315. #define SICRH_GPIOSEL_0 (0 << 8)
  316. #define SICRH_GPIOSEL_1 (1 << 8)
  317. #define SICRH_TMROBI_V3P3 (0 << 4)
  318. #define SICRH_TMROBI_V2P5 (1 << 4)
  319. #define SICRH_TSOBI1_V3P3 (0 << 1)
  320. #define SICRH_TSOBI1_V2P5 (1 << 1)
  321. #define SICRH_TSOBI2_V3P3 (0 << 0)
  322. #define SICRH_TSOBI2_V2P5 (1 << 0)
  323. #elif defined(CONFIG_ARCH_MPC8309)
  324. /* SICR_1 */
  325. #define SICR_1_UART1_UART1S (0 << (30-2))
  326. #define SICR_1_UART1_UART1RTS (1 << (30-2))
  327. #define SICR_1_I2C_I2C (0 << (30-4))
  328. #define SICR_1_I2C_CKSTOP (1 << (30-4))
  329. #define SICR_1_IRQ_A_IRQ (0 << (30-6))
  330. #define SICR_1_IRQ_A_MCP (1 << (30-6))
  331. #define SICR_1_IRQ_B_IRQ (0 << (30-8))
  332. #define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
  333. #define SICR_1_GPIO_A_GPIO (0 << (30-10))
  334. #define SICR_1_GPIO_A_SD (2 << (30-10))
  335. #define SICR_1_GPIO_A_DDR (3 << (30-10))
  336. #define SICR_1_GPIO_B_GPIO (0 << (30-12))
  337. #define SICR_1_GPIO_B_SD (2 << (30-12))
  338. #define SICR_1_GPIO_B_QE (3 << (30-12))
  339. #define SICR_1_GPIO_C_GPIO (0 << (30-14))
  340. #define SICR_1_GPIO_C_CAN (1 << (30-14))
  341. #define SICR_1_GPIO_C_DDR (2 << (30-14))
  342. #define SICR_1_GPIO_C_LCS (3 << (30-14))
  343. #define SICR_1_GPIO_D_GPIO (0 << (30-16))
  344. #define SICR_1_GPIO_D_CAN (1 << (30-16))
  345. #define SICR_1_GPIO_D_DDR (2 << (30-16))
  346. #define SICR_1_GPIO_D_LCS (3 << (30-16))
  347. #define SICR_1_GPIO_E_GPIO (0 << (30-18))
  348. #define SICR_1_GPIO_E_CAN (1 << (30-18))
  349. #define SICR_1_GPIO_E_DDR (2 << (30-18))
  350. #define SICR_1_GPIO_E_LCS (3 << (30-18))
  351. #define SICR_1_GPIO_F_GPIO (0 << (30-20))
  352. #define SICR_1_GPIO_F_CAN (1 << (30-20))
  353. #define SICR_1_GPIO_F_CK (2 << (30-20))
  354. #define SICR_1_USB_A_USBDR (0 << (30-22))
  355. #define SICR_1_USB_A_UART2S (1 << (30-22))
  356. #define SICR_1_USB_B_USBDR (0 << (30-24))
  357. #define SICR_1_USB_B_UART2S (1 << (30-24))
  358. #define SICR_1_USB_B_UART2RTS (2 << (30-24))
  359. #define SICR_1_USB_C_USBDR (0 << (30-26))
  360. #define SICR_1_USB_C_QE_EXT (3 << (30-26))
  361. #define SICR_1_FEC1_FEC1 (0 << (30-28))
  362. #define SICR_1_FEC1_GTM (1 << (30-28))
  363. #define SICR_1_FEC1_GPIO (2 << (30-28))
  364. #define SICR_1_FEC2_FEC2 (0 << (30-30))
  365. #define SICR_1_FEC2_GTM (1 << (30-30))
  366. #define SICR_1_FEC2_GPIO (2 << (30-30))
  367. /* SICR_2 */
  368. #define SICR_2_FEC3_FEC3 (0 << (30-0))
  369. #define SICR_2_FEC3_TMR (1 << (30-0))
  370. #define SICR_2_FEC3_GPIO (2 << (30-0))
  371. #define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
  372. #define SICR_2_HDLC1_A_GPIO (1 << (30-2))
  373. #define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
  374. #define SICR_2_ELBC_A_LA (0 << (30-4))
  375. #define SICR_2_ELBC_B_LCLK (0 << (30-6))
  376. #define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
  377. #define SICR_2_HDLC2_A_GPIO (0 << (30-8))
  378. #define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
  379. /* bits 10-11 unused */
  380. #define SICR_2_USB_D_USBDR (0 << (30-12))
  381. #define SICR_2_USB_D_GPIO (2 << (30-12))
  382. #define SICR_2_USB_D_QE_BRG (3 << (30-12))
  383. #define SICR_2_PCI_PCI (0 << (30-14))
  384. #define SICR_2_PCI_CPCI_HS (2 << (30-14))
  385. #define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
  386. #define SICR_2_HDLC1_B_GPIO (1 << (30-16))
  387. #define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
  388. #define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
  389. #define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
  390. #define SICR_2_HDLC1_C_GPIO (1 << (30-18))
  391. #define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
  392. #define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
  393. #define SICR_2_HDLC2_B_GPIO (1 << (30-20))
  394. #define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
  395. #define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
  396. #define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
  397. #define SICR_2_HDLC2_C_GPIO (1 << (30-22))
  398. #define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
  399. #define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
  400. #define SICR_2_QUIESCE_B (0 << (30-24))
  401. #endif
  402. /*
  403. * SWCRR - System Watchdog Control Register
  404. */
  405. /* Register offset to immr */
  406. #define SWCRR 0x0204
  407. /* Software Watchdog Time Count */
  408. #define SWCRR_SWTC 0xFFFF0000
  409. /* Watchdog Enable bit */
  410. #define SWCRR_SWEN 0x00000004
  411. /* Software Watchdog Reset/Interrupt Select bit */
  412. #define SWCRR_SWRI 0x00000002
  413. /* Software Watchdog Counter Prescale bit */
  414. #define SWCRR_SWPR 0x00000001
  415. #define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \
  416. SWCRR_SWRI | SWCRR_SWPR))
  417. /*
  418. * SWCNR - System Watchdog Counter Register
  419. */
  420. /* Register offset to immr */
  421. #define SWCNR 0x0208
  422. /* Software Watchdog Count mask */
  423. #define SWCNR_SWCN 0x0000FFFF
  424. #define SWCNR_RES ~(SWCNR_SWCN)
  425. /*
  426. * SWSRR - System Watchdog Service Register
  427. */
  428. /* Register offset to immr */
  429. #define SWSRR 0x020E
  430. /*
  431. * ACR - Arbiter Configuration Register
  432. */
  433. #define ACR_COREDIS 0x10000000 /* Core disable */
  434. #define ACR_COREDIS_SHIFT (31-7)
  435. #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
  436. #define ACR_PIPE_DEP_SHIFT (31-15)
  437. #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
  438. #define ACR_PCI_RPTCNT_SHIFT (31-19)
  439. #define ACR_RPTCNT 0x00000700 /* Repeat count */
  440. #define ACR_RPTCNT_SHIFT (31-23)
  441. #define ACR_APARK 0x00000030 /* Address parking */
  442. #define ACR_APARK_SHIFT (31-27)
  443. #define ACR_PARKM 0x0000000F /* Parking master */
  444. #define ACR_PARKM_SHIFT (31-31)
  445. /*
  446. * ATR - Arbiter Timers Register
  447. */
  448. #define ATR_DTO 0x00FF0000 /* Data time out */
  449. #define ATR_DTO_SHIFT 16
  450. #define ATR_ATO 0x000000FF /* Address time out */
  451. #define ATR_ATO_SHIFT 0
  452. /*
  453. * AER - Arbiter Event Register
  454. */
  455. #define AER_ETEA 0x00000020 /* Transfer error */
  456. /* Reserved transfer type */
  457. #define AER_RES 0x00000010
  458. /* External control word transfer type */
  459. #define AER_ECW 0x00000008
  460. /* Address Only transfer type */
  461. #define AER_AO 0x00000004
  462. #define AER_DTO 0x00000002 /* Data time out */
  463. #define AER_ATO 0x00000001 /* Address time out */
  464. /*
  465. * AEATR - Arbiter Event Address Register
  466. */
  467. #define AEATR_EVENT 0x07000000 /* Event type */
  468. #define AEATR_EVENT_SHIFT 24
  469. #define AEATR_MSTR_ID 0x001F0000 /* Master Id */
  470. #define AEATR_MSTR_ID_SHIFT 16
  471. #define AEATR_TBST 0x00000800 /* Transfer burst */
  472. #define AEATR_TBST_SHIFT 11
  473. #define AEATR_TSIZE 0x00000700 /* Transfer Size */
  474. #define AEATR_TSIZE_SHIFT 8
  475. #define AEATR_TTYPE 0x0000001F /* Transfer Type */
  476. #define AEATR_TTYPE_SHIFT 0
  477. /*
  478. * HRCWL - Hard Reset Configuration Word Low
  479. */
  480. #define HRCWL_LBIUCM 0x80000000
  481. #define HRCWL_LBIUCM_SHIFT 31
  482. #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
  483. #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
  484. #define HRCWL_DDRCM 0x40000000
  485. #define HRCWL_DDRCM_SHIFT 30
  486. #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
  487. #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
  488. #define HRCWL_SPMF 0x0f000000
  489. #define HRCWL_SPMF_SHIFT 24
  490. #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
  491. #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
  492. #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
  493. #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
  494. #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
  495. #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
  496. #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
  497. #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
  498. #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
  499. #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
  500. #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
  501. #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
  502. #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
  503. #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
  504. #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
  505. #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
  506. #define HRCWL_VCO_BYPASS 0x00000000
  507. #define HRCWL_VCO_1X2 0x00000000
  508. #define HRCWL_VCO_1X4 0x00200000
  509. #define HRCWL_VCO_1X8 0x00400000
  510. #define HRCWL_COREPLL 0x007F0000
  511. #define HRCWL_COREPLL_SHIFT 16
  512. #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
  513. #define HRCWL_CORE_TO_CSB_1X1 0x00020000
  514. #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
  515. #define HRCWL_CORE_TO_CSB_2X1 0x00040000
  516. #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
  517. #define HRCWL_CORE_TO_CSB_3X1 0x00060000
  518. #if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X)
  519. #define HRCWL_CEVCOD 0x000000C0
  520. #define HRCWL_CEVCOD_SHIFT 6
  521. #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
  522. #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
  523. #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
  524. #define HRCWL_CEPDF 0x00000020
  525. #define HRCWL_CEPDF_SHIFT 5
  526. #define HRCWL_CE_PLL_DIV_1X1 0x00000000
  527. #define HRCWL_CE_PLL_DIV_2X1 0x00000020
  528. #define HRCWL_CEPMF 0x0000001F
  529. #define HRCWL_CEPMF_SHIFT 0
  530. #define HRCWL_CE_TO_PLL_1X16_ 0x00000000
  531. #define HRCWL_CE_TO_PLL_1X2 0x00000002
  532. #define HRCWL_CE_TO_PLL_1X3 0x00000003
  533. #define HRCWL_CE_TO_PLL_1X4 0x00000004
  534. #define HRCWL_CE_TO_PLL_1X5 0x00000005
  535. #define HRCWL_CE_TO_PLL_1X6 0x00000006
  536. #define HRCWL_CE_TO_PLL_1X7 0x00000007
  537. #define HRCWL_CE_TO_PLL_1X8 0x00000008
  538. #define HRCWL_CE_TO_PLL_1X9 0x00000009
  539. #define HRCWL_CE_TO_PLL_1X10 0x0000000A
  540. #define HRCWL_CE_TO_PLL_1X11 0x0000000B
  541. #define HRCWL_CE_TO_PLL_1X12 0x0000000C
  542. #define HRCWL_CE_TO_PLL_1X13 0x0000000D
  543. #define HRCWL_CE_TO_PLL_1X14 0x0000000E
  544. #define HRCWL_CE_TO_PLL_1X15 0x0000000F
  545. #define HRCWL_CE_TO_PLL_1X16 0x00000010
  546. #define HRCWL_CE_TO_PLL_1X17 0x00000011
  547. #define HRCWL_CE_TO_PLL_1X18 0x00000012
  548. #define HRCWL_CE_TO_PLL_1X19 0x00000013
  549. #define HRCWL_CE_TO_PLL_1X20 0x00000014
  550. #define HRCWL_CE_TO_PLL_1X21 0x00000015
  551. #define HRCWL_CE_TO_PLL_1X22 0x00000016
  552. #define HRCWL_CE_TO_PLL_1X23 0x00000017
  553. #define HRCWL_CE_TO_PLL_1X24 0x00000018
  554. #define HRCWL_CE_TO_PLL_1X25 0x00000019
  555. #define HRCWL_CE_TO_PLL_1X26 0x0000001A
  556. #define HRCWL_CE_TO_PLL_1X27 0x0000001B
  557. #define HRCWL_CE_TO_PLL_1X28 0x0000001C
  558. #define HRCWL_CE_TO_PLL_1X29 0x0000001D
  559. #define HRCWL_CE_TO_PLL_1X30 0x0000001E
  560. #define HRCWL_CE_TO_PLL_1X31 0x0000001F
  561. #elif defined(CONFIG_ARCH_MPC8308)
  562. #define HRCWL_SVCOD 0x30000000
  563. #define HRCWL_SVCOD_SHIFT 28
  564. #define HRCWL_SVCOD_DIV_2 0x00000000
  565. #define HRCWL_SVCOD_DIV_4 0x10000000
  566. #define HRCWL_SVCOD_DIV_8 0x20000000
  567. #define HRCWL_SVCOD_DIV_1 0x30000000
  568. #elif defined(CONFIG_ARCH_MPC837X)
  569. #define HRCWL_SVCOD 0x30000000
  570. #define HRCWL_SVCOD_SHIFT 28
  571. #define HRCWL_SVCOD_DIV_4 0x00000000
  572. #define HRCWL_SVCOD_DIV_8 0x10000000
  573. #define HRCWL_SVCOD_DIV_2 0x20000000
  574. #define HRCWL_SVCOD_DIV_1 0x30000000
  575. #elif defined(CONFIG_ARCH_MPC8309)
  576. #define HRCWL_CEVCOD 0x000000C0
  577. #define HRCWL_CEVCOD_SHIFT 6
  578. /*
  579. * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
  580. * these are different than with 8360, 832x
  581. */
  582. #define HRCWL_CE_PLL_VCO_DIV_2 0x00000000
  583. #define HRCWL_CE_PLL_VCO_DIV_4 0x00000040
  584. #define HRCWL_CE_PLL_VCO_DIV_8 0x00000080
  585. #define HRCWL_CEPDF 0x00000020
  586. #define HRCWL_CEPDF_SHIFT 5
  587. #define HRCWL_CE_PLL_DIV_1X1 0x00000000
  588. #define HRCWL_CE_PLL_DIV_2X1 0x00000020
  589. #define HRCWL_CEPMF 0x0000001F
  590. #define HRCWL_CEPMF_SHIFT 0
  591. #define HRCWL_CE_TO_PLL_1X16_ 0x00000000
  592. #define HRCWL_CE_TO_PLL_1X2 0x00000002
  593. #define HRCWL_CE_TO_PLL_1X3 0x00000003
  594. #define HRCWL_CE_TO_PLL_1X4 0x00000004
  595. #define HRCWL_CE_TO_PLL_1X5 0x00000005
  596. #define HRCWL_CE_TO_PLL_1X6 0x00000006
  597. #define HRCWL_CE_TO_PLL_1X7 0x00000007
  598. #define HRCWL_CE_TO_PLL_1X8 0x00000008
  599. #define HRCWL_CE_TO_PLL_1X9 0x00000009
  600. #define HRCWL_CE_TO_PLL_1X10 0x0000000A
  601. #define HRCWL_CE_TO_PLL_1X11 0x0000000B
  602. #define HRCWL_CE_TO_PLL_1X12 0x0000000C
  603. #define HRCWL_CE_TO_PLL_1X13 0x0000000D
  604. #define HRCWL_CE_TO_PLL_1X14 0x0000000E
  605. #define HRCWL_CE_TO_PLL_1X15 0x0000000F
  606. #define HRCWL_CE_TO_PLL_1X16 0x00000010
  607. #define HRCWL_CE_TO_PLL_1X17 0x00000011
  608. #define HRCWL_CE_TO_PLL_1X18 0x00000012
  609. #define HRCWL_CE_TO_PLL_1X19 0x00000013
  610. #define HRCWL_CE_TO_PLL_1X20 0x00000014
  611. #define HRCWL_CE_TO_PLL_1X21 0x00000015
  612. #define HRCWL_CE_TO_PLL_1X22 0x00000016
  613. #define HRCWL_CE_TO_PLL_1X23 0x00000017
  614. #define HRCWL_CE_TO_PLL_1X24 0x00000018
  615. #define HRCWL_CE_TO_PLL_1X25 0x00000019
  616. #define HRCWL_CE_TO_PLL_1X26 0x0000001A
  617. #define HRCWL_CE_TO_PLL_1X27 0x0000001B
  618. #define HRCWL_CE_TO_PLL_1X28 0x0000001C
  619. #define HRCWL_CE_TO_PLL_1X29 0x0000001D
  620. #define HRCWL_CE_TO_PLL_1X30 0x0000001E
  621. #define HRCWL_CE_TO_PLL_1X31 0x0000001F
  622. #define HRCWL_SVCOD 0x30000000
  623. #define HRCWL_SVCOD_SHIFT 28
  624. #define HRCWL_SVCOD_DIV_2 0x00000000
  625. #define HRCWL_SVCOD_DIV_4 0x10000000
  626. #define HRCWL_SVCOD_DIV_8 0x20000000
  627. #define HRCWL_SVCOD_DIV_1 0x30000000
  628. #endif
  629. /*
  630. * HRCWH - Hardware Reset Configuration Word High
  631. */
  632. #define HRCWH_PCI_HOST 0x80000000
  633. #define HRCWH_PCI_HOST_SHIFT 31
  634. #define HRCWH_PCI_AGENT 0x00000000
  635. #if defined(CONFIG_ARCH_MPC834X)
  636. #define HRCWH_32_BIT_PCI 0x00000000
  637. #define HRCWH_64_BIT_PCI 0x40000000
  638. #endif
  639. #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
  640. #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
  641. #define HRCWH_PCI_ARBITER_DISABLE 0x00000000
  642. #define HRCWH_PCI_ARBITER_ENABLE 0x20000000
  643. #if defined(CONFIG_ARCH_MPC834X)
  644. #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
  645. #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
  646. #elif defined(CONFIG_ARCH_MPC8360)
  647. #define HRCWH_PCICKDRV_DISABLE 0x00000000
  648. #define HRCWH_PCICKDRV_ENABLE 0x10000000
  649. #endif
  650. #define HRCWH_CORE_DISABLE 0x08000000
  651. #define HRCWH_CORE_ENABLE 0x00000000
  652. #define HRCWH_FROM_0X00000100 0x00000000
  653. #define HRCWH_FROM_0XFFF00100 0x04000000
  654. #define HRCWH_BOOTSEQ_DISABLE 0x00000000
  655. #define HRCWH_BOOTSEQ_NORMAL 0x01000000
  656. #define HRCWH_BOOTSEQ_EXTENDED 0x02000000
  657. #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
  658. #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
  659. #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
  660. #define HRCWH_ROM_LOC_PCI1 0x00100000
  661. #if defined(CONFIG_ARCH_MPC834X)
  662. #define HRCWH_ROM_LOC_PCI2 0x00200000
  663. #endif
  664. #if defined(CONFIG_ARCH_MPC837X)
  665. #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
  666. #endif
  667. #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
  668. #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
  669. #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
  670. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  671. defined(CONFIG_ARCH_MPC837X)
  672. #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
  673. #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
  674. #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
  675. #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
  676. #define HRCWH_RL_EXT_LEGACY 0x00000000
  677. #define HRCWH_RL_EXT_NAND 0x00040000
  678. #define HRCWH_TSEC1M_MASK 0x0000E000
  679. #define HRCWH_TSEC1M_IN_MII 0x00000000
  680. #define HRCWH_TSEC1M_IN_RMII 0x00002000
  681. #define HRCWH_TSEC1M_IN_RGMII 0x00006000
  682. #define HRCWH_TSEC1M_IN_RTBI 0x0000A000
  683. #define HRCWH_TSEC1M_IN_SGMII 0x0000C000
  684. #define HRCWH_TSEC2M_MASK 0x00001C00
  685. #define HRCWH_TSEC2M_IN_MII 0x00000000
  686. #define HRCWH_TSEC2M_IN_RMII 0x00000400
  687. #define HRCWH_TSEC2M_IN_RGMII 0x00000C00
  688. #define HRCWH_TSEC2M_IN_RTBI 0x00001400
  689. #define HRCWH_TSEC2M_IN_SGMII 0x00001800
  690. #endif
  691. #if defined(CONFIG_ARCH_MPC834X)
  692. #define HRCWH_TSEC1M_IN_RGMII 0x00000000
  693. #define HRCWH_TSEC1M_IN_RTBI 0x00004000
  694. #define HRCWH_TSEC1M_IN_GMII 0x00008000
  695. #define HRCWH_TSEC1M_IN_TBI 0x0000C000
  696. #define HRCWH_TSEC2M_IN_RGMII 0x00000000
  697. #define HRCWH_TSEC2M_IN_RTBI 0x00001000
  698. #define HRCWH_TSEC2M_IN_GMII 0x00002000
  699. #define HRCWH_TSEC2M_IN_TBI 0x00003000
  700. #endif
  701. #if defined(CONFIG_ARCH_MPC8360)
  702. #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
  703. #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
  704. #endif
  705. #define HRCWH_BIG_ENDIAN 0x00000000
  706. #define HRCWH_LITTLE_ENDIAN 0x00000008
  707. #define HRCWH_LALE_NORMAL 0x00000000
  708. #define HRCWH_LALE_EARLY 0x00000004
  709. #define HRCWH_LDP_SET 0x00000000
  710. #define HRCWH_LDP_CLEAR 0x00000002
  711. /*
  712. * RSR - Reset Status Register
  713. */
  714. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  715. defined(CONFIG_ARCH_MPC837X)
  716. #define RSR_RSTSRC 0xF0000000 /* Reset source */
  717. #define RSR_RSTSRC_SHIFT 28
  718. #else
  719. #define RSR_RSTSRC 0xE0000000 /* Reset source */
  720. #define RSR_RSTSRC_SHIFT 29
  721. #endif
  722. #define RSR_BSF 0x00010000 /* Boot seq. fail */
  723. #define RSR_BSF_SHIFT 16
  724. /* software soft reset */
  725. #define RSR_SWSR 0x00002000
  726. #define RSR_SWSR_SHIFT 13
  727. /* software hard reset */
  728. #define RSR_SWHR 0x00001000
  729. #define RSR_SWHR_SHIFT 12
  730. #define RSR_JHRS 0x00000200 /* jtag hreset */
  731. #define RSR_JHRS_SHIFT 9
  732. /* jtag sreset status */
  733. #define RSR_JSRS 0x00000100
  734. #define RSR_JSRS_SHIFT 8
  735. /* checkstop reset status */
  736. #define RSR_CSHR 0x00000010
  737. #define RSR_CSHR_SHIFT 4
  738. /* software watchdog reset status */
  739. #define RSR_SWRS 0x00000008
  740. #define RSR_SWRS_SHIFT 3
  741. /* bus monitop reset status */
  742. #define RSR_BMRS 0x00000004
  743. #define RSR_BMRS_SHIFT 2
  744. #define RSR_SRS 0x00000002 /* soft reset status */
  745. #define RSR_SRS_SHIFT 1
  746. #define RSR_HRS 0x00000001 /* hard reset status */
  747. #define RSR_HRS_SHIFT 0
  748. #define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
  749. RSR_SWHR | RSR_JHRS | \
  750. RSR_JSRS | RSR_CSHR | \
  751. RSR_SWRS | RSR_BMRS | \
  752. RSR_SRS | RSR_HRS))
  753. /*
  754. * RMR - Reset Mode Register
  755. */
  756. /* checkstop reset enable */
  757. #define RMR_CSRE 0x00000001
  758. #define RMR_CSRE_SHIFT 0
  759. #define RMR_RES ~(RMR_CSRE)
  760. /*
  761. * RCR - Reset Control Register
  762. */
  763. /* software hard reset */
  764. #define RCR_SWHR 0x00000002
  765. /* software soft reset */
  766. #define RCR_SWSR 0x00000001
  767. #define RCR_RES ~(RCR_SWHR | RCR_SWSR)
  768. /*
  769. * RCER - Reset Control Enable Register
  770. */
  771. /* software hard reset */
  772. #define RCER_CRE 0x00000001
  773. #define RCER_RES ~(RCER_CRE)
  774. /*
  775. * SPMR - System PLL Mode Register
  776. */
  777. #define SPMR_LBIUCM 0x80000000
  778. #define SPMR_LBIUCM_SHIFT 31
  779. #define SPMR_DDRCM 0x40000000
  780. #define SPMR_DDRCM_SHIFT 30
  781. #define SPMR_SPMF 0x0F000000
  782. #define SPMR_SPMF_SHIFT 24
  783. #define SPMR_CKID 0x00800000
  784. #define SPMR_CKID_SHIFT 23
  785. #define SPMR_COREPLL 0x007F0000
  786. #define SPMR_COREPLL_SHIFT 16
  787. #define SPMR_CEVCOD 0x000000C0
  788. #define SPMR_CEVCOD_SHIFT 6
  789. #define SPMR_CEPDF 0x00000020
  790. #define SPMR_CEPDF_SHIFT 5
  791. #define SPMR_CEPMF 0x0000001F
  792. #define SPMR_CEPMF_SHIFT 0
  793. /*
  794. * OCCR - Output Clock Control Register
  795. */
  796. #define OCCR_PCICOE0 0x80000000
  797. #define OCCR_PCICOE1 0x40000000
  798. #define OCCR_PCICOE2 0x20000000
  799. #define OCCR_PCICOE3 0x10000000
  800. #define OCCR_PCICOE4 0x08000000
  801. #define OCCR_PCICOE5 0x04000000
  802. #define OCCR_PCICOE6 0x02000000
  803. #define OCCR_PCICOE7 0x01000000
  804. #define OCCR_PCICD0 0x00800000
  805. #define OCCR_PCICD1 0x00400000
  806. #define OCCR_PCICD2 0x00200000
  807. #define OCCR_PCICD3 0x00100000
  808. #define OCCR_PCICD4 0x00080000
  809. #define OCCR_PCICD5 0x00040000
  810. #define OCCR_PCICD6 0x00020000
  811. #define OCCR_PCICD7 0x00010000
  812. #define OCCR_PCI1CR 0x00000002
  813. #define OCCR_PCI2CR 0x00000001
  814. #define OCCR_PCICR OCCR_PCI1CR
  815. /*
  816. * SCCR - System Clock Control Register
  817. */
  818. #define SCCR_ENCCM 0x03000000
  819. #define SCCR_ENCCM_SHIFT 24
  820. #define SCCR_ENCCM_0 0x00000000
  821. #define SCCR_ENCCM_1 0x01000000
  822. #define SCCR_ENCCM_2 0x02000000
  823. #define SCCR_ENCCM_3 0x03000000
  824. #define SCCR_PCICM 0x00010000
  825. #define SCCR_PCICM_SHIFT 16
  826. #if defined(CONFIG_ARCH_MPC834X)
  827. /* SCCR bits - MPC834X specific */
  828. #define SCCR_TSEC1CM 0xc0000000
  829. #define SCCR_TSEC1CM_SHIFT 30
  830. #define SCCR_TSEC1CM_0 0x00000000
  831. #define SCCR_TSEC1CM_1 0x40000000
  832. #define SCCR_TSEC1CM_2 0x80000000
  833. #define SCCR_TSEC1CM_3 0xC0000000
  834. #define SCCR_TSEC2CM 0x30000000
  835. #define SCCR_TSEC2CM_SHIFT 28
  836. #define SCCR_TSEC2CM_0 0x00000000
  837. #define SCCR_TSEC2CM_1 0x10000000
  838. #define SCCR_TSEC2CM_2 0x20000000
  839. #define SCCR_TSEC2CM_3 0x30000000
  840. /* The MPH must have the same clock ratio as DR, unless its clock disabled */
  841. #define SCCR_USBMPHCM 0x00c00000
  842. #define SCCR_USBMPHCM_SHIFT 22
  843. #define SCCR_USBDRCM 0x00300000
  844. #define SCCR_USBDRCM_SHIFT 20
  845. #define SCCR_USBCM 0x00f00000
  846. #define SCCR_USBCM_SHIFT 20
  847. #define SCCR_USBCM_0 0x00000000
  848. #define SCCR_USBCM_1 0x00500000
  849. #define SCCR_USBCM_2 0x00A00000
  850. #define SCCR_USBCM_3 0x00F00000
  851. #elif defined(CONFIG_ARCH_MPC8313)
  852. /* TSEC1 bits are for TSEC2 as well */
  853. #define SCCR_TSEC1CM 0xc0000000
  854. #define SCCR_TSEC1CM_SHIFT 30
  855. #define SCCR_TSEC1CM_0 0x00000000
  856. #define SCCR_TSEC1CM_1 0x40000000
  857. #define SCCR_TSEC1CM_2 0x80000000
  858. #define SCCR_TSEC1CM_3 0xC0000000
  859. #define SCCR_TSEC1ON 0x20000000
  860. #define SCCR_TSEC1ON_SHIFT 29
  861. #define SCCR_TSEC2ON 0x10000000
  862. #define SCCR_TSEC2ON_SHIFT 28
  863. #define SCCR_USBDRCM 0x00300000
  864. #define SCCR_USBDRCM_SHIFT 20
  865. #define SCCR_USBDRCM_0 0x00000000
  866. #define SCCR_USBDRCM_1 0x00100000
  867. #define SCCR_USBDRCM_2 0x00200000
  868. #define SCCR_USBDRCM_3 0x00300000
  869. #elif defined(CONFIG_ARCH_MPC8308)
  870. /* SCCR bits - MPC8315/MPC8308 specific */
  871. #define SCCR_TSEC1CM 0xc0000000
  872. #define SCCR_TSEC1CM_SHIFT 30
  873. #define SCCR_TSEC1CM_0 0x00000000
  874. #define SCCR_TSEC1CM_1 0x40000000
  875. #define SCCR_TSEC1CM_2 0x80000000
  876. #define SCCR_TSEC1CM_3 0xC0000000
  877. #define SCCR_TSEC2CM 0x30000000
  878. #define SCCR_TSEC2CM_SHIFT 28
  879. #define SCCR_TSEC2CM_0 0x00000000
  880. #define SCCR_TSEC2CM_1 0x10000000
  881. #define SCCR_TSEC2CM_2 0x20000000
  882. #define SCCR_TSEC2CM_3 0x30000000
  883. #define SCCR_SDHCCM 0x0c000000
  884. #define SCCR_SDHCCM_SHIFT 26
  885. #define SCCR_SDHCCM_0 0x00000000
  886. #define SCCR_SDHCCM_1 0x04000000
  887. #define SCCR_SDHCCM_2 0x08000000
  888. #define SCCR_SDHCCM_3 0x0c000000
  889. #define SCCR_USBDRCM 0x00c00000
  890. #define SCCR_USBDRCM_SHIFT 22
  891. #define SCCR_USBDRCM_0 0x00000000
  892. #define SCCR_USBDRCM_1 0x00400000
  893. #define SCCR_USBDRCM_2 0x00800000
  894. #define SCCR_USBDRCM_3 0x00c00000
  895. #define SCCR_SATA1CM 0x00003000
  896. #define SCCR_SATA1CM_SHIFT 12
  897. #define SCCR_SATACM 0x00003c00
  898. #define SCCR_SATACM_SHIFT 10
  899. #define SCCR_SATACM_0 0x00000000
  900. #define SCCR_SATACM_1 0x00001400
  901. #define SCCR_SATACM_2 0x00002800
  902. #define SCCR_SATACM_3 0x00003c00
  903. #define SCCR_TDMCM 0x00000030
  904. #define SCCR_TDMCM_SHIFT 4
  905. #define SCCR_TDMCM_0 0x00000000
  906. #define SCCR_TDMCM_1 0x00000010
  907. #define SCCR_TDMCM_2 0x00000020
  908. #define SCCR_TDMCM_3 0x00000030
  909. #elif defined(CONFIG_ARCH_MPC837X)
  910. /* SCCR bits - MPC837X specific */
  911. #define SCCR_TSEC1CM 0xc0000000
  912. #define SCCR_TSEC1CM_SHIFT 30
  913. #define SCCR_TSEC1CM_0 0x00000000
  914. #define SCCR_TSEC1CM_1 0x40000000
  915. #define SCCR_TSEC1CM_2 0x80000000
  916. #define SCCR_TSEC1CM_3 0xC0000000
  917. #define SCCR_TSEC2CM 0x30000000
  918. #define SCCR_TSEC2CM_SHIFT 28
  919. #define SCCR_TSEC2CM_0 0x00000000
  920. #define SCCR_TSEC2CM_1 0x10000000
  921. #define SCCR_TSEC2CM_2 0x20000000
  922. #define SCCR_TSEC2CM_3 0x30000000
  923. #define SCCR_SDHCCM 0x0c000000
  924. #define SCCR_SDHCCM_SHIFT 26
  925. #define SCCR_SDHCCM_0 0x00000000
  926. #define SCCR_SDHCCM_1 0x04000000
  927. #define SCCR_SDHCCM_2 0x08000000
  928. #define SCCR_SDHCCM_3 0x0c000000
  929. #define SCCR_USBDRCM 0x00c00000
  930. #define SCCR_USBDRCM_SHIFT 22
  931. #define SCCR_USBDRCM_0 0x00000000
  932. #define SCCR_USBDRCM_1 0x00400000
  933. #define SCCR_USBDRCM_2 0x00800000
  934. #define SCCR_USBDRCM_3 0x00c00000
  935. /* All of the four SATA controllers must have the same clock ratio */
  936. #define SCCR_SATA1CM 0x000000c0
  937. #define SCCR_SATA1CM_SHIFT 6
  938. #define SCCR_SATACM 0x000000ff
  939. #define SCCR_SATACM_SHIFT 0
  940. #define SCCR_SATACM_0 0x00000000
  941. #define SCCR_SATACM_1 0x00000055
  942. #define SCCR_SATACM_2 0x000000aa
  943. #define SCCR_SATACM_3 0x000000ff
  944. #elif defined(CONFIG_ARCH_MPC8309)
  945. /* SCCR bits - MPC8309 specific */
  946. #define SCCR_SDHCCM 0x0c000000
  947. #define SCCR_SDHCCM_SHIFT 26
  948. #define SCCR_SDHCCM_0 0x00000000
  949. #define SCCR_SDHCCM_1 0x04000000
  950. #define SCCR_SDHCCM_2 0x08000000
  951. #define SCCR_SDHCCM_3 0x0c000000
  952. #define SCCR_USBDRCM 0x00c00000
  953. #define SCCR_USBDRCM_SHIFT 22
  954. #define SCCR_USBDRCM_0 0x00000000
  955. #define SCCR_USBDRCM_1 0x00400000
  956. #define SCCR_USBDRCM_2 0x00800000
  957. #define SCCR_USBDRCM_3 0x00c00000
  958. #endif
  959. #define SCCR_PCIEXP1CM 0x00300000
  960. #define SCCR_PCIEXP1CM_SHIFT 20
  961. #define SCCR_PCIEXP1CM_0 0x00000000
  962. #define SCCR_PCIEXP1CM_1 0x00100000
  963. #define SCCR_PCIEXP1CM_2 0x00200000
  964. #define SCCR_PCIEXP1CM_3 0x00300000
  965. #define SCCR_PCIEXP2CM 0x000c0000
  966. #define SCCR_PCIEXP2CM_SHIFT 18
  967. #define SCCR_PCIEXP2CM_0 0x00000000
  968. #define SCCR_PCIEXP2CM_1 0x00040000
  969. #define SCCR_PCIEXP2CM_2 0x00080000
  970. #define SCCR_PCIEXP2CM_3 0x000c0000
  971. /*
  972. * CSn_BDNS - Chip Select memory Bounds Register
  973. */
  974. #define CSBNDS_SA 0x00FF0000
  975. #define CSBNDS_SA_SHIFT 8
  976. #define CSBNDS_EA 0x000000FF
  977. #define CSBNDS_EA_SHIFT 24
  978. #ifndef CONFIG_MPC83XX_SDRAM
  979. /*
  980. * CSn_CONFIG - Chip Select Configuration Register
  981. */
  982. #define CSCONFIG_EN 0x80000000
  983. #define CSCONFIG_AP 0x00800000
  984. #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X)
  985. #define CSCONFIG_ODT_RD_NEVER 0x00000000
  986. #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
  987. #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
  988. #define CSCONFIG_ODT_RD_ALL 0x00400000
  989. #define CSCONFIG_ODT_WR_NEVER 0x00000000
  990. #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
  991. #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
  992. #define CSCONFIG_ODT_WR_ALL 0x00040000
  993. #elif defined(CONFIG_ARCH_MPC832X)
  994. #define CSCONFIG_ODT_RD_CFG 0x00400000
  995. #define CSCONFIG_ODT_WR_CFG 0x00040000
  996. #elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X)
  997. #define CSCONFIG_ODT_RD_NEVER 0x00000000
  998. #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
  999. #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
  1000. #define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000
  1001. #define CSCONFIG_ODT_RD_ALL 0x00400000
  1002. #define CSCONFIG_ODT_WR_NEVER 0x00000000
  1003. #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
  1004. #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
  1005. #define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000
  1006. #define CSCONFIG_ODT_WR_ALL 0x00040000
  1007. #endif
  1008. #define CSCONFIG_BANK_BIT_3 0x00004000
  1009. #define CSCONFIG_ROW_BIT 0x00000700
  1010. #define CSCONFIG_ROW_BIT_12 0x00000000
  1011. #define CSCONFIG_ROW_BIT_13 0x00000100
  1012. #define CSCONFIG_ROW_BIT_14 0x00000200
  1013. #define CSCONFIG_COL_BIT 0x00000007
  1014. #define CSCONFIG_COL_BIT_8 0x00000000
  1015. #define CSCONFIG_COL_BIT_9 0x00000001
  1016. #define CSCONFIG_COL_BIT_10 0x00000002
  1017. #define CSCONFIG_COL_BIT_11 0x00000003
  1018. /*
  1019. * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
  1020. */
  1021. #define TIMING_CFG0_RWT 0xC0000000
  1022. #define TIMING_CFG0_RWT_SHIFT 30
  1023. #define TIMING_CFG0_WRT 0x30000000
  1024. #define TIMING_CFG0_WRT_SHIFT 28
  1025. #define TIMING_CFG0_RRT 0x0C000000
  1026. #define TIMING_CFG0_RRT_SHIFT 26
  1027. #define TIMING_CFG0_WWT 0x03000000
  1028. #define TIMING_CFG0_WWT_SHIFT 24
  1029. #define TIMING_CFG0_ACT_PD_EXIT 0x00700000
  1030. #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20
  1031. #define TIMING_CFG0_PRE_PD_EXIT 0x00070000
  1032. #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16
  1033. #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00
  1034. #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8
  1035. #define TIMING_CFG0_MRS_CYC 0x0000000F
  1036. #define TIMING_CFG0_MRS_CYC_SHIFT 0
  1037. /*
  1038. * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
  1039. */
  1040. #define TIMING_CFG1_PRETOACT 0x70000000
  1041. #define TIMING_CFG1_PRETOACT_SHIFT 28
  1042. #define TIMING_CFG1_ACTTOPRE 0x0F000000
  1043. #define TIMING_CFG1_ACTTOPRE_SHIFT 24
  1044. #define TIMING_CFG1_ACTTORW 0x00700000
  1045. #define TIMING_CFG1_ACTTORW_SHIFT 20
  1046. #define TIMING_CFG1_CASLAT 0x00070000
  1047. #define TIMING_CFG1_CASLAT_SHIFT 16
  1048. #define TIMING_CFG1_REFREC 0x0000F000
  1049. #define TIMING_CFG1_REFREC_SHIFT 12
  1050. #define TIMING_CFG1_WRREC 0x00000700
  1051. #define TIMING_CFG1_WRREC_SHIFT 8
  1052. #define TIMING_CFG1_ACTTOACT 0x00000070
  1053. #define TIMING_CFG1_ACTTOACT_SHIFT 4
  1054. #define TIMING_CFG1_WRTORD 0x00000007
  1055. #define TIMING_CFG1_WRTORD_SHIFT 0
  1056. #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
  1057. #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
  1058. #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */
  1059. #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */
  1060. #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */
  1061. #define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */
  1062. #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */
  1063. /*
  1064. * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  1065. */
  1066. #define TIMING_CFG2_CPO 0x0F800000
  1067. #define TIMING_CFG2_CPO_SHIFT 23
  1068. #define TIMING_CFG2_ACSM 0x00080000
  1069. #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
  1070. #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
  1071. /* default (= CASLAT + 1) */
  1072. #define TIMING_CFG2_CPO_DEF 0x00000000
  1073. #define TIMING_CFG2_ADD_LAT 0x70000000
  1074. #define TIMING_CFG2_ADD_LAT_SHIFT 28
  1075. #define TIMING_CFG2_WR_LAT_DELAY 0x00380000
  1076. #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19
  1077. #define TIMING_CFG2_RD_TO_PRE 0x0000E000
  1078. #define TIMING_CFG2_RD_TO_PRE_SHIFT 13
  1079. #define TIMING_CFG2_CKE_PLS 0x000001C0
  1080. #define TIMING_CFG2_CKE_PLS_SHIFT 6
  1081. #define TIMING_CFG2_FOUR_ACT 0x0000003F
  1082. #define TIMING_CFG2_FOUR_ACT_SHIFT 0
  1083. /*
  1084. * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
  1085. */
  1086. #define TIMING_CFG3_EXT_REFREC 0x00070000
  1087. #define TIMING_CFG3_EXT_REFREC_SHIFT 16
  1088. /*
  1089. * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
  1090. */
  1091. #define SDRAM_CFG_MEM_EN 0x80000000
  1092. #define SDRAM_CFG_SREN 0x40000000
  1093. #define SDRAM_CFG_ECC_EN 0x20000000
  1094. #define SDRAM_CFG_RD_EN 0x10000000
  1095. #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
  1096. #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
  1097. #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
  1098. #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
  1099. #define SDRAM_CFG_DYN_PWR 0x00200000
  1100. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
  1101. #define SDRAM_CFG_DBW_MASK 0x00180000
  1102. #define SDRAM_CFG_DBW_16 0x00100000
  1103. #define SDRAM_CFG_DBW_32 0x00080000
  1104. #else
  1105. #define SDRAM_CFG_32_BE 0x00080000
  1106. #endif
  1107. #if !defined(CONFIG_ARCH_MPC8308)
  1108. #define SDRAM_CFG_8_BE 0x00040000
  1109. #endif
  1110. #define SDRAM_CFG_NCAP 0x00020000
  1111. #define SDRAM_CFG_2T_EN 0x00008000
  1112. #define SDRAM_CFG_HSE 0x00000008
  1113. #define SDRAM_CFG_BI 0x00000001
  1114. /*
  1115. * DDR_SDRAM_MODE - DDR SDRAM Mode Register
  1116. */
  1117. #define SDRAM_MODE_ESD 0xFFFF0000
  1118. #define SDRAM_MODE_ESD_SHIFT 16
  1119. #define SDRAM_MODE_SD 0x0000FFFF
  1120. #define SDRAM_MODE_SD_SHIFT 0
  1121. /* select extended mode reg */
  1122. #define DDR_MODE_EXT_MODEREG 0x4000
  1123. /* operating mode, mask */
  1124. #define DDR_MODE_EXT_OPMODE 0x3FF8
  1125. #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
  1126. /* QFC / compatibility, mask */
  1127. #define DDR_MODE_QFC 0x0004
  1128. /* compatible to older SDRAMs */
  1129. #define DDR_MODE_QFC_COMP 0x0000
  1130. /* weak drivers */
  1131. #define DDR_MODE_WEAK 0x0002
  1132. /* disable DLL */
  1133. #define DDR_MODE_DLL_DIS 0x0001
  1134. /* CAS latency, mask */
  1135. #define DDR_MODE_CASLAT 0x0070
  1136. #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
  1137. #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
  1138. #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
  1139. #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
  1140. /* sequential burst */
  1141. #define DDR_MODE_BTYPE_SEQ 0x0000
  1142. /* interleaved burst */
  1143. #define DDR_MODE_BTYPE_ILVD 0x0008
  1144. #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
  1145. #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
  1146. /* exact value for 7.8125us */
  1147. #define DDR_REFINT_166MHZ_7US 1302
  1148. /* use 256 cycles as a starting point */
  1149. #define DDR_BSTOPRE 256
  1150. /* select mode register */
  1151. #define DDR_MODE_MODEREG 0x0000
  1152. /*
  1153. * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
  1154. */
  1155. #define SDRAM_INTERVAL_REFINT 0x3FFF0000
  1156. #define SDRAM_INTERVAL_REFINT_SHIFT 16
  1157. #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
  1158. /*
  1159. * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
  1160. */
  1161. #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
  1162. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
  1163. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
  1164. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
  1165. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
  1166. /*
  1167. * ECC_ERR_INJECT - Memory data path error injection mask ECC
  1168. */
  1169. /* ECC Mirror Byte */
  1170. #define ECC_ERR_INJECT_EMB (0x80000000 >> 22)
  1171. /* Error Injection Enable */
  1172. #define ECC_ERR_INJECT_EIEN (0x80000000 >> 23)
  1173. /* ECC Erroe Injection Enable */
  1174. #define ECC_ERR_INJECT_EEIM (0xff000000 >> 24)
  1175. #define ECC_ERR_INJECT_EEIM_SHIFT 0
  1176. /*
  1177. * CAPTURE_ECC - Memory data path read capture ECC
  1178. */
  1179. #define CAPTURE_ECC_ECE (0xff000000 >> 24)
  1180. #define CAPTURE_ECC_ECE_SHIFT 0
  1181. /*
  1182. * ERR_DETECT - Memory error detect
  1183. */
  1184. /* Multiple Memory Errors */
  1185. #define ECC_ERROR_DETECT_MME (0x80000000 >> 0)
  1186. /* Multiple-Bit Error */
  1187. #define ECC_ERROR_DETECT_MBE (0x80000000 >> 28)
  1188. /* Single-Bit ECC Error Pickup */
  1189. #define ECC_ERROR_DETECT_SBE (0x80000000 >> 29)
  1190. /* Memory Select Error */
  1191. #define ECC_ERROR_DETECT_MSE (0x80000000 >> 31)
  1192. /*
  1193. * ERR_DISABLE - Memory error disable
  1194. */
  1195. /* Multiple-Bit ECC Error Disable */
  1196. #define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28)
  1197. /* Sinle-Bit ECC Error disable */
  1198. #define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29)
  1199. /* Memory Select Error Disable */
  1200. #define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31)
  1201. #define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \
  1202. ECC_ERROR_DISABLE_SBED | \
  1203. ECC_ERROR_DISABLE_MBED))
  1204. /*
  1205. * ERR_INT_EN - Memory error interrupt enable
  1206. */
  1207. /* Multiple-Bit ECC Error Interrupt Enable */
  1208. #define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28)
  1209. /* Single-Bit ECC Error Interrupt Enable */
  1210. #define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29)
  1211. /* Memory Select Error Interrupt Enable */
  1212. #define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31)
  1213. #define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \
  1214. ECC_ERR_INT_EN_SBEE | \
  1215. ECC_ERR_INT_EN_MSEE))
  1216. /*
  1217. * CAPTURE_ATTRIBUTES - Memory error attributes capture
  1218. */
  1219. /* Data Beat Num */
  1220. #define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1)
  1221. #define ECC_CAPT_ATTR_BNUM_SHIFT 28
  1222. /* Transaction Size */
  1223. #define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6)
  1224. #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
  1225. #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
  1226. #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
  1227. #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
  1228. #define ECC_CAPT_ATTR_TSIZ_SHIFT 24
  1229. /* Transaction Source */
  1230. #define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11)
  1231. #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
  1232. #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
  1233. #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
  1234. #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
  1235. #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
  1236. #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
  1237. #define ECC_CAPT_ATTR_TSRC_I2C 0x9
  1238. #define ECC_CAPT_ATTR_TSRC_JTAG 0xA
  1239. #define ECC_CAPT_ATTR_TSRC_PCI1 0xD
  1240. #define ECC_CAPT_ATTR_TSRC_PCI2 0xE
  1241. #define ECC_CAPT_ATTR_TSRC_DMA 0xF
  1242. #define ECC_CAPT_ATTR_TSRC_SHIFT 16
  1243. /* Transaction Type */
  1244. #define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18)
  1245. #define ECC_CAPT_ATTR_TTYP_WRITE 0x1
  1246. #define ECC_CAPT_ATTR_TTYP_READ 0x2
  1247. #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
  1248. #define ECC_CAPT_ATTR_TTYP_SHIFT 12
  1249. #define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */
  1250. /*
  1251. * ERR_SBE - Single bit ECC memory error management
  1252. */
  1253. /* Single-Bit Error Threshold 0..255 */
  1254. #define ECC_ERROR_MAN_SBET (0xff000000 >> 8)
  1255. #define ECC_ERROR_MAN_SBET_SHIFT 16
  1256. /* Single Bit Error Counter 0..255 */
  1257. #define ECC_ERROR_MAN_SBEC (0xff000000 >> 24)
  1258. #define ECC_ERROR_MAN_SBEC_SHIFT 0
  1259. #endif /* !CONFIG_MPC83XX_SDRAM */
  1260. /*
  1261. * PCI_CONFIG_ADDRESS - PCI Config Address Register
  1262. */
  1263. #define PCI_CONFIG_ADDRESS_EN 0x80000000
  1264. #define PCI_CONFIG_ADDRESS_BN_SHIFT 16
  1265. #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
  1266. #define PCI_CONFIG_ADDRESS_DN_SHIFT 11
  1267. #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
  1268. #define PCI_CONFIG_ADDRESS_FN_SHIFT 8
  1269. #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
  1270. #define PCI_CONFIG_ADDRESS_RN_SHIFT 0
  1271. #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
  1272. /*
  1273. * POTAR - PCI Outbound Translation Address Register
  1274. */
  1275. #define POTAR_TA_MASK 0x000fffff
  1276. /*
  1277. * POBAR - PCI Outbound Base Address Register
  1278. */
  1279. #define POBAR_BA_MASK 0x000fffff
  1280. /*
  1281. * POCMR - PCI Outbound Comparision Mask Register
  1282. */
  1283. #define POCMR_EN 0x80000000
  1284. /* 0-memory space 1-I/O space */
  1285. #define POCMR_IO 0x40000000
  1286. #define POCMR_SE 0x20000000 /* streaming enable */
  1287. #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
  1288. #define POCMR_CM_MASK 0x000fffff
  1289. #define POCMR_CM_4G 0x00000000
  1290. #define POCMR_CM_2G 0x00080000
  1291. #define POCMR_CM_1G 0x000C0000
  1292. #define POCMR_CM_512M 0x000E0000
  1293. #define POCMR_CM_256M 0x000F0000
  1294. #define POCMR_CM_128M 0x000F8000
  1295. #define POCMR_CM_64M 0x000FC000
  1296. #define POCMR_CM_32M 0x000FE000
  1297. #define POCMR_CM_16M 0x000FF000
  1298. #define POCMR_CM_8M 0x000FF800
  1299. #define POCMR_CM_4M 0x000FFC00
  1300. #define POCMR_CM_2M 0x000FFE00
  1301. #define POCMR_CM_1M 0x000FFF00
  1302. #define POCMR_CM_512K 0x000FFF80
  1303. #define POCMR_CM_256K 0x000FFFC0
  1304. #define POCMR_CM_128K 0x000FFFE0
  1305. #define POCMR_CM_64K 0x000FFFF0
  1306. #define POCMR_CM_32K 0x000FFFF8
  1307. #define POCMR_CM_16K 0x000FFFFC
  1308. #define POCMR_CM_8K 0x000FFFFE
  1309. #define POCMR_CM_4K 0x000FFFFF
  1310. /*
  1311. * PITAR - PCI Inbound Translation Address Register
  1312. */
  1313. #define PITAR_TA_MASK 0x000fffff
  1314. /*
  1315. * PIBAR - PCI Inbound Base/Extended Address Register
  1316. */
  1317. #define PIBAR_MASK 0xffffffff
  1318. #define PIEBAR_EBA_MASK 0x000fffff
  1319. /*
  1320. * PIWAR - PCI Inbound Windows Attributes Register
  1321. */
  1322. #define PIWAR_EN 0x80000000
  1323. #define PIWAR_PF 0x20000000
  1324. #define PIWAR_RTT_MASK 0x000f0000
  1325. #define PIWAR_RTT_NO_SNOOP 0x00040000
  1326. #define PIWAR_RTT_SNOOP 0x00050000
  1327. #define PIWAR_WTT_MASK 0x0000f000
  1328. #define PIWAR_WTT_NO_SNOOP 0x00004000
  1329. #define PIWAR_WTT_SNOOP 0x00005000
  1330. #define PIWAR_IWS_MASK 0x0000003F
  1331. #define PIWAR_IWS_4K 0x0000000B
  1332. #define PIWAR_IWS_8K 0x0000000C
  1333. #define PIWAR_IWS_16K 0x0000000D
  1334. #define PIWAR_IWS_32K 0x0000000E
  1335. #define PIWAR_IWS_64K 0x0000000F
  1336. #define PIWAR_IWS_128K 0x00000010
  1337. #define PIWAR_IWS_256K 0x00000011
  1338. #define PIWAR_IWS_512K 0x00000012
  1339. #define PIWAR_IWS_1M 0x00000013
  1340. #define PIWAR_IWS_2M 0x00000014
  1341. #define PIWAR_IWS_4M 0x00000015
  1342. #define PIWAR_IWS_8M 0x00000016
  1343. #define PIWAR_IWS_16M 0x00000017
  1344. #define PIWAR_IWS_32M 0x00000018
  1345. #define PIWAR_IWS_64M 0x00000019
  1346. #define PIWAR_IWS_128M 0x0000001A
  1347. #define PIWAR_IWS_256M 0x0000001B
  1348. #define PIWAR_IWS_512M 0x0000001C
  1349. #define PIWAR_IWS_1G 0x0000001D
  1350. #define PIWAR_IWS_2G 0x0000001E
  1351. /*
  1352. * PMCCR1 - PCI Configuration Register 1
  1353. */
  1354. #define PMCCR1_POWER_OFF 0x00000020
  1355. #ifndef CONFIG_RAM
  1356. /*
  1357. * DDRCDR - DDR Control Driver Register
  1358. */
  1359. #define DDRCDR_DHC_EN 0x80000000
  1360. #define DDRCDR_EN 0x40000000
  1361. #define DDRCDR_PZ 0x3C000000
  1362. #define DDRCDR_PZ_MAXZ 0x00000000
  1363. #define DDRCDR_PZ_HIZ 0x20000000
  1364. #define DDRCDR_PZ_NOMZ 0x30000000
  1365. #define DDRCDR_PZ_LOZ 0x38000000
  1366. #define DDRCDR_PZ_MINZ 0x3C000000
  1367. #define DDRCDR_NZ 0x3C000000
  1368. #define DDRCDR_NZ_MAXZ 0x00000000
  1369. #define DDRCDR_NZ_HIZ 0x02000000
  1370. #define DDRCDR_NZ_NOMZ 0x03000000
  1371. #define DDRCDR_NZ_LOZ 0x03800000
  1372. #define DDRCDR_NZ_MINZ 0x03C00000
  1373. #define DDRCDR_ODT 0x00080000
  1374. #define DDRCDR_DDR_CFG 0x00040000
  1375. #define DDRCDR_M_ODR 0x00000002
  1376. #define DDRCDR_Q_DRN 0x00000001
  1377. #endif /* !CONFIG_RAM */
  1378. /*
  1379. * PCIE Bridge Register
  1380. */
  1381. #define PEX_CSB_CTRL_OBPIOE 0x00000001
  1382. #define PEX_CSB_CTRL_IBPIOE 0x00000002
  1383. #define PEX_CSB_CTRL_WDMAE 0x00000004
  1384. #define PEX_CSB_CTRL_RDMAE 0x00000008
  1385. #define PEX_CSB_OBCTRL_PIOE 0x00000001
  1386. #define PEX_CSB_OBCTRL_MEMWE 0x00000002
  1387. #define PEX_CSB_OBCTRL_IOWE 0x00000004
  1388. #define PEX_CSB_OBCTRL_CFGWE 0x00000008
  1389. #define PEX_CSB_IBCTRL_PIOE 0x00000001
  1390. #define PEX_OWAR_EN 0x00000001
  1391. #define PEX_OWAR_TYPE_CFG 0x00000000
  1392. #define PEX_OWAR_TYPE_IO 0x00000002
  1393. #define PEX_OWAR_TYPE_MEM 0x00000004
  1394. #define PEX_OWAR_RLXO 0x00000008
  1395. #define PEX_OWAR_NANP 0x00000010
  1396. #define PEX_OWAR_SIZE 0xFFFFF000
  1397. #define PEX_IWAR_EN 0x00000001
  1398. #define PEX_IWAR_TYPE_INT 0x00000000
  1399. #define PEX_IWAR_TYPE_PF 0x00000004
  1400. #define PEX_IWAR_TYPE_NO_PF 0x00000006
  1401. #define PEX_IWAR_NSOV 0x00000008
  1402. #define PEX_IWAR_NSNP 0x00000010
  1403. #define PEX_IWAR_SIZE 0xFFFFF000
  1404. #define PEX_IWAR_SIZE_1M 0x000FF000
  1405. #define PEX_IWAR_SIZE_2M 0x001FF000
  1406. #define PEX_IWAR_SIZE_4M 0x003FF000
  1407. #define PEX_IWAR_SIZE_8M 0x007FF000
  1408. #define PEX_IWAR_SIZE_16M 0x00FFF000
  1409. #define PEX_IWAR_SIZE_32M 0x01FFF000
  1410. #define PEX_IWAR_SIZE_64M 0x03FFF000
  1411. #define PEX_IWAR_SIZE_128M 0x07FFF000
  1412. #define PEX_IWAR_SIZE_256M 0x0FFFF000
  1413. #define PEX_GCLK_RATIO 0x440
  1414. #ifndef __ASSEMBLY__
  1415. struct pci_region;
  1416. void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
  1417. void mpc83xx_pcislave_unlock(int bus);
  1418. void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
  1419. #endif
  1420. #endif /* __MPC83XX_H__ */