fsl_sec.h 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Common internal memory map for some Freescale SoCs
  4. *
  5. * Copyright 2014 Freescale Semiconductor, Inc.
  6. * Copyright 2018 NXP
  7. */
  8. #ifndef __FSL_SEC_H
  9. #define __FSL_SEC_H
  10. #include <common.h>
  11. #include <asm/io.h>
  12. #ifdef CONFIG_SYS_FSL_SEC_LE
  13. #define sec_in32(a) in_le32((ulong *)(ulong)a)
  14. #define sec_out32(a, v) out_le32((ulong *)(ulong)a, v)
  15. #define sec_in16(a) in_le16(a)
  16. #define sec_clrbits32 clrbits_le32
  17. #define sec_setbits32 setbits_le32
  18. #elif defined(CONFIG_SYS_FSL_SEC_BE)
  19. #define sec_in32(a) in_be32(a)
  20. #define sec_out32(a, v) out_be32(a, v)
  21. #define sec_in16(a) in_be16(a)
  22. #define sec_clrbits32 clrbits_be32
  23. #define sec_setbits32 setbits_be32
  24. #elif defined(CONFIG_SYS_FSL_HAS_SEC)
  25. #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
  26. #endif
  27. #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
  28. /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
  29. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  30. /* RNG4 TRNG test registers */
  31. struct rng4tst {
  32. #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
  33. #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
  34. both entropy shifter and
  35. statistical checker */
  36. #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
  37. entropy shifter and
  38. statistical checker */
  39. #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
  40. entropy shifter, raw data
  41. in statistical checker */
  42. #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
  43. u32 rtmctl; /* misc. control register */
  44. u32 rtscmisc; /* statistical check misc. register */
  45. u32 rtpkrrng; /* poker range register */
  46. #define RTSDCTL_ENT_DLY_MIN 3200
  47. #define RTSDCTL_ENT_DLY_MAX 12800
  48. union {
  49. u32 rtpkrmax; /* PRGM=1: poker max. limit register */
  50. u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
  51. };
  52. #define RTSDCTL_ENT_DLY_SHIFT 16
  53. #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
  54. u32 rtsdctl; /* seed control register */
  55. union {
  56. u32 rtsblim; /* PRGM=1: sparse bit limit register */
  57. u32 rttotsam; /* PRGM=0: total samples register */
  58. };
  59. u32 rtfreqmin; /* frequency count min. limit register */
  60. #define RTFRQMAX_DISABLE (1 << 20)
  61. union {
  62. u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
  63. u32 rtfreqcnt; /* PRGM=0: freq. count register */
  64. };
  65. u32 rsvd1[40];
  66. #define RDSTA_IF(idx) (0x00000001 << (idx))
  67. #define RDSTA_PR(idx) (0x00000010 << (idx))
  68. #define RDSTA_MASK (RDSTA_PR(1) | RDSTA_PR(0) | RDSTA_IF(1) | RDSTA_IF(0))
  69. #define RDSTA_SKVN 0x40000000
  70. u32 rdsta; /*RNG DRNG Status Register*/
  71. u32 rsvd2[15];
  72. };
  73. /* Version registers (Era 10+) */
  74. struct version_regs {
  75. u32 crca; /* CRCA_VERSION */
  76. u32 afha; /* AFHA_VERSION */
  77. u32 kfha; /* KFHA_VERSION */
  78. u32 pkha; /* PKHA_VERSION */
  79. u32 aesa; /* AESA_VERSION */
  80. u32 mdha; /* MDHA_VERSION */
  81. u32 desa; /* DESA_VERSION */
  82. u32 snw8a; /* SNW8A_VERSION */
  83. u32 snw9a; /* SNW9A_VERSION */
  84. u32 zuce; /* ZUCE_VERSION */
  85. u32 zuca; /* ZUCA_VERSION */
  86. u32 ccha; /* CCHA_VERSION */
  87. u32 ptha; /* PTHA_VERSION */
  88. u32 rng; /* RNG_VERSION */
  89. u32 trng; /* TRNG_VERSION */
  90. u32 aaha; /* AAHA_VERSION */
  91. u32 rsvd[10];
  92. u32 sr; /* SR_VERSION */
  93. u32 dma; /* DMA_VERSION */
  94. u32 ai; /* AI_VERSION */
  95. u32 qi; /* QI_VERSION */
  96. u32 jr; /* JR_VERSION */
  97. u32 deco; /* DECO_VERSION */
  98. };
  99. #define CHA_VER_NUM_MASK 0x000000ff
  100. #define CHA_VER_MISC_SHIFT 8
  101. #define CHA_VER_MISC_MASK 0x0000ff00
  102. #define CHA_VER_REV_SHIFT 16
  103. #define CHA_VER_REV_MASK 0x00ff0000
  104. #define CHA_VER_VID_SHIFT 24
  105. #define CHA_VER_VID_MASK 0xff000000
  106. typedef struct ccsr_sec {
  107. u32 res0;
  108. u32 mcfgr; /* Master CFG Register */
  109. u8 res1[0x4];
  110. u32 scfgr;
  111. struct {
  112. u32 ms; /* Job Ring LIODN Register, MS */
  113. u32 ls; /* Job Ring LIODN Register, LS */
  114. } jrliodnr[4];
  115. u8 res2[0x2c];
  116. u32 jrstartr; /* Job Ring Start Register */
  117. struct {
  118. u32 ms; /* RTIC LIODN Register, MS */
  119. u32 ls; /* RTIC LIODN Register, LS */
  120. } rticliodnr[4];
  121. u8 res3[0x1c];
  122. u32 decorr; /* DECO Request Register */
  123. struct {
  124. u32 ms; /* DECO LIODN Register, MS */
  125. u32 ls; /* DECO LIODN Register, LS */
  126. } decoliodnr[16];
  127. u32 dar; /* DECO Avail Register */
  128. u32 drr; /* DECO Reset Register */
  129. u8 res5[0x4d8];
  130. struct rng4tst rng; /* RNG Registers */
  131. u8 res6[0x780];
  132. struct version_regs vreg; /* version registers since era 10 */
  133. u8 res7[0xa0];
  134. u32 crnr_ms; /* CHA Revision Number Register, MS */
  135. u32 crnr_ls; /* CHA Revision Number Register, LS */
  136. u32 ctpr_ms; /* Compile Time Parameters Register, MS */
  137. u32 ctpr_ls; /* Compile Time Parameters Register, LS */
  138. u8 res8[0x10];
  139. u32 far_ms; /* Fault Address Register, MS */
  140. u32 far_ls; /* Fault Address Register, LS */
  141. u32 falr; /* Fault Address LIODN Register */
  142. u32 fadr; /* Fault Address Detail Register */
  143. u8 res9[0x4];
  144. u32 csta; /* CAAM Status Register */
  145. u32 smpart; /* Secure Memory Partition Parameters */
  146. u32 smvid; /* Secure Memory Version ID */
  147. u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
  148. u32 ccbvid; /* CHA Cluster Block Version ID Register */
  149. u32 chavid_ms; /* CHA Version ID Register, MS */
  150. u32 chavid_ls; /* CHA Version ID Register, LS */
  151. u32 chanum_ms; /* CHA Number Register, MS */
  152. u32 chanum_ls; /* CHA Number Register, LS */
  153. u32 secvid_ms; /* SEC Version ID Register, MS */
  154. u32 secvid_ls; /* SEC Version ID Register, LS */
  155. #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
  156. u8 res10[0x6f020];
  157. #else
  158. u8 res10[0x6020];
  159. #endif
  160. u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
  161. u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
  162. #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
  163. u8 res11[0x8ffd8];
  164. #else
  165. u8 res11[0x8fd8];
  166. #endif
  167. } ccsr_sec_t;
  168. #define SEC_CTPR_MS_AXI_LIODN 0x08000000
  169. #define SEC_CTPR_MS_QI 0x02000000
  170. #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
  171. #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
  172. #define SEC_RVID_MA 0x0f000000
  173. #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
  174. #define SEC_CHANUM_MS_JRNUM_SHIFT 28
  175. #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
  176. #define SEC_CHANUM_MS_DECONUM_SHIFT 24
  177. #define SEC_SECVID_MS_IPID_MASK 0xffff0000
  178. #define SEC_SECVID_MS_IPID_SHIFT 16
  179. #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
  180. #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
  181. #define SEC_CCBVID_ERA_MASK 0xff000000
  182. #define SEC_CCBVID_ERA_SHIFT 24
  183. #define SEC_SCFGR_RDBENABLE 0x00000400
  184. #define SEC_SCFGR_VIRT_EN 0x00008000
  185. #define SEC_CHAVID_LS_RNG_SHIFT 16
  186. #define SEC_CHAVID_RNG_LS_MASK 0x000f0000
  187. #define CONFIG_JRSTARTR_JR0 0x00000001
  188. struct jr_regs {
  189. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  190. !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  191. defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
  192. u32 irba_l;
  193. u32 irba_h;
  194. #else
  195. u32 irba_h;
  196. u32 irba_l;
  197. #endif
  198. u32 rsvd1;
  199. u32 irs;
  200. u32 rsvd2;
  201. u32 irsa;
  202. u32 rsvd3;
  203. u32 irja;
  204. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  205. !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  206. defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
  207. u32 orba_l;
  208. u32 orba_h;
  209. #else
  210. u32 orba_h;
  211. u32 orba_l;
  212. #endif
  213. u32 rsvd4;
  214. u32 ors;
  215. u32 rsvd5;
  216. u32 orjr;
  217. u32 rsvd6;
  218. u32 orsf;
  219. u32 rsvd7;
  220. u32 jrsta;
  221. u32 rsvd8;
  222. u32 jrint;
  223. u32 jrcfg0;
  224. u32 jrcfg1;
  225. u32 rsvd9;
  226. u32 irri;
  227. u32 rsvd10;
  228. u32 orwi;
  229. u32 rsvd11;
  230. u32 jrcr;
  231. };
  232. /*
  233. * Scatter Gather Entry - Specifies the the Scatter Gather Format
  234. * related information
  235. */
  236. struct sg_entry {
  237. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  238. !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  239. defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
  240. uint32_t addr_lo; /* Memory Address - lo */
  241. uint32_t addr_hi; /* Memory Address of start of buffer - hi */
  242. #else
  243. uint32_t addr_hi; /* Memory Address of start of buffer - hi */
  244. uint32_t addr_lo; /* Memory Address - lo */
  245. #endif
  246. uint32_t len_flag; /* Length of the data in the frame */
  247. #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
  248. #define SG_ENTRY_EXTENSION_BIT 0x80000000
  249. #define SG_ENTRY_FINAL_BIT 0x40000000
  250. uint32_t bpid_offset;
  251. #define SG_ENTRY_BPID_MASK 0x00FF0000
  252. #define SG_ENTRY_BPID_SHIFT 16
  253. #define SG_ENTRY_OFFSET_MASK 0x00001FFF
  254. #define SG_ENTRY_OFFSET_SHIFT 0
  255. };
  256. #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  257. defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
  258. /* Job Ring Base Address */
  259. #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
  260. /* Secure Memory Offset varies accross versions */
  261. #define SM_V1_OFFSET 0x0f4
  262. #define SM_V2_OFFSET 0xa00
  263. /*Secure Memory Versioning */
  264. #define SMVID_V2 0x20105
  265. #define SM_VERSION(x) ({typeof(x) _x = x; \
  266. _x < SMVID_V2 ? 1 : (_x < 0x20300 ? 2 : 3); })
  267. #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
  268. /* CAAM Job Ring 0 Registers */
  269. /* Secure Memory Partition Owner register */
  270. #define SMCSJR_PO (3 << 6)
  271. /* JR Allocation Error */
  272. #define SMCSJR_AERR (3 << 12)
  273. /* Secure memory partition 0 page 0 owner register */
  274. #define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
  275. /* Secure memory command register */
  276. #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
  277. /* Secure memory command status register */
  278. #define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
  279. /* Secure memory access permissions register */
  280. #define CAAM_SMAPJR(v, jr, y) \
  281. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
  282. /* Secure memory access group 2 register */
  283. #define CAAM_SMAG2JR(v, jr, y) \
  284. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
  285. /* Secure memory access group 1 register */
  286. #define CAAM_SMAG1JR(v, jr, y) \
  287. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
  288. /* Commands and macros for secure memory */
  289. #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4)
  290. #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC)
  291. #define SM_PERM(v) (v == 1 ? 0x10 : 0x4)
  292. #define SM_GROUP2(v) ({typeof(v) _v = v; \
  293. _v == 1 ? 0x14 : (_v == 2 ? 0x8 : 0xC); })
  294. #define SM_GROUP1(v) ({typeof(v) _v = v; \
  295. _v == 1 ? 0x18 : (_v == 2 ? 0xC : 0x8); })
  296. #define CMD_PAGE_ALLOC 0x1
  297. #define CMD_PAGE_DEALLOC 0x2
  298. #define CMD_PART_DEALLOC 0x3
  299. #define CMD_INQUIRY 0x5
  300. #define CMD_COMPLETE (3 << 14)
  301. #define PAGE_AVAILABLE 0
  302. #define PAGE_OWNED (3 << 6)
  303. #define PAGE(x) (x << 16)
  304. #define PARTITION(x) (x << 8)
  305. #define PARTITION_OWNER(x) (0x3 << (x*2))
  306. /* Address of secure 4kbyte pages */
  307. #define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
  308. #define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
  309. #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
  310. #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
  311. #ifdef CONFIG_IMX8M
  312. #define JR_MID (1) /* Matches ATF configuration */
  313. #define KS_G1 (0x10000 << JR_MID) /* CAAM only */
  314. #define PERM (0xB080) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */
  315. #else
  316. #define JR_MID (2) /* Matches ROM configuration */
  317. #define KS_G1 BIT(JR_MID) /* CAAM only */
  318. #define PERM (0xB008) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */
  319. #endif /* CONFIG_IMX8M */
  320. /* HAB WRAPPED KEY header */
  321. #define WRP_HDR_SIZE 0x08
  322. #define HDR_TAG 0x81
  323. #define HDR_PAR 0x41
  324. /* HAB WRAPPED KEY Data */
  325. #define HAB_MOD 0x66
  326. #define HAB_ALG 0x55
  327. #define HAB_FLG 0x00
  328. /* Partition and Page IDs */
  329. #define PARTITION_1 1
  330. #define PAGE_1 1
  331. #define ERROR_IN_PAGE_ALLOC 1
  332. #define ECONSTRJDESC -1
  333. #endif
  334. #define FSL_CAAM_MP_PUBK_BYTES 64
  335. #define FSL_CAAM_MP_PRVK_BYTES 32
  336. #define FSL_CAAM_MP_MES_DGST_BYTES 32
  337. #define FSL_CAAM_ORSR_JRa_OFFSET 0x102c
  338. #define FSL_CAAM_MAX_JR_SIZE 4
  339. /* blob_dek:
  340. * Encapsulates the src in a secure blob and stores it dst
  341. * @src: reference to the plaintext
  342. * @dst: reference to the output adrress
  343. * @len: size in bytes of src
  344. * @return: 0 on success, error otherwise
  345. */
  346. int blob_dek(const u8 *src, u8 *dst, u8 len);
  347. int gen_mppubk(u8 *dst);
  348. int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d);
  349. #if defined(CONFIG_ARCH_C29X)
  350. int sec_init_idx(uint8_t);
  351. #endif
  352. int sec_init(void);
  353. u8 caam_get_era(void);
  354. #endif
  355. #endif /* __FSL_SEC_H */