board_f.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2002-2006
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Marius Groeger <mgroeger@sysgo.de>
  10. */
  11. #include <common.h>
  12. #include <bloblist.h>
  13. #include <bootstage.h>
  14. #include <clock_legacy.h>
  15. #include <console.h>
  16. #include <cpu.h>
  17. #include <cpu_func.h>
  18. #include <dm.h>
  19. #include <env.h>
  20. #include <env_internal.h>
  21. #include <fdtdec.h>
  22. #include <fs.h>
  23. #include <hang.h>
  24. #include <i2c.h>
  25. #include <init.h>
  26. #include <initcall.h>
  27. #include <lcd.h>
  28. #include <log.h>
  29. #include <malloc.h>
  30. #include <mapmem.h>
  31. #include <os.h>
  32. #include <post.h>
  33. #include <relocate.h>
  34. #include <serial.h>
  35. #ifdef CONFIG_SPL
  36. #include <spl.h>
  37. #endif
  38. #include <status_led.h>
  39. #include <sysreset.h>
  40. #include <timer.h>
  41. #include <trace.h>
  42. #include <video.h>
  43. #include <watchdog.h>
  44. #include <asm/cache.h>
  45. #ifdef CONFIG_MACH_TYPE
  46. #include <asm/mach-types.h>
  47. #endif
  48. #if defined(CONFIG_MP) && defined(CONFIG_PPC)
  49. #include <asm/mp.h>
  50. #endif
  51. #include <asm/global_data.h>
  52. #include <asm/io.h>
  53. #include <asm/sections.h>
  54. #include <dm/root.h>
  55. #include <linux/errno.h>
  56. /*
  57. * Pointer to initial global data area
  58. *
  59. * Here we initialize it if needed.
  60. */
  61. #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
  62. #undef XTRN_DECLARE_GLOBAL_DATA_PTR
  63. #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
  64. DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
  65. #else
  66. DECLARE_GLOBAL_DATA_PTR;
  67. #endif
  68. /*
  69. * TODO(sjg@chromium.org): IMO this code should be
  70. * refactored to a single function, something like:
  71. *
  72. * void led_set_state(enum led_colour_t colour, int on);
  73. */
  74. /************************************************************************
  75. * Coloured LED functionality
  76. ************************************************************************
  77. * May be supplied by boards if desired
  78. */
  79. __weak void coloured_LED_init(void) {}
  80. __weak void red_led_on(void) {}
  81. __weak void red_led_off(void) {}
  82. __weak void green_led_on(void) {}
  83. __weak void green_led_off(void) {}
  84. __weak void yellow_led_on(void) {}
  85. __weak void yellow_led_off(void) {}
  86. __weak void blue_led_on(void) {}
  87. __weak void blue_led_off(void) {}
  88. /*
  89. * Why is gd allocated a register? Prior to reloc it might be better to
  90. * just pass it around to each function in this file?
  91. *
  92. * After reloc one could argue that it is hardly used and doesn't need
  93. * to be in a register. Or if it is it should perhaps hold pointers to all
  94. * global data for all modules, so that post-reloc we can avoid the massive
  95. * literal pool we get on ARM. Or perhaps just encourage each module to use
  96. * a structure...
  97. */
  98. #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
  99. static int init_func_watchdog_init(void)
  100. {
  101. # if defined(CONFIG_HW_WATCHDOG) && \
  102. (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
  103. defined(CONFIG_SH) || \
  104. defined(CONFIG_DESIGNWARE_WATCHDOG) || \
  105. defined(CONFIG_IMX_WATCHDOG))
  106. hw_watchdog_init();
  107. puts(" Watchdog enabled\n");
  108. # endif
  109. WATCHDOG_RESET();
  110. return 0;
  111. }
  112. int init_func_watchdog_reset(void)
  113. {
  114. WATCHDOG_RESET();
  115. return 0;
  116. }
  117. #endif /* CONFIG_WATCHDOG */
  118. __weak void board_add_ram_info(int use_default)
  119. {
  120. /* please define platform specific board_add_ram_info() */
  121. }
  122. static int init_baud_rate(void)
  123. {
  124. gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
  125. return 0;
  126. }
  127. static int display_text_info(void)
  128. {
  129. #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
  130. ulong bss_start, bss_end, text_base;
  131. bss_start = (ulong)&__bss_start;
  132. bss_end = (ulong)&__bss_end;
  133. #ifdef CONFIG_SYS_TEXT_BASE
  134. text_base = CONFIG_SYS_TEXT_BASE;
  135. #else
  136. text_base = CONFIG_SYS_MONITOR_BASE;
  137. #endif
  138. debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
  139. text_base, bss_start, bss_end);
  140. #endif
  141. return 0;
  142. }
  143. #ifdef CONFIG_SYSRESET
  144. static int print_resetinfo(void)
  145. {
  146. struct udevice *dev;
  147. char status[256];
  148. int ret;
  149. ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
  150. if (ret) {
  151. debug("%s: No sysreset device found (error: %d)\n",
  152. __func__, ret);
  153. /* Not all boards have sysreset drivers available during early
  154. * boot, so don't fail if one can't be found.
  155. */
  156. return 0;
  157. }
  158. if (!sysreset_get_status(dev, status, sizeof(status)))
  159. printf("%s", status);
  160. return 0;
  161. }
  162. #endif
  163. #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
  164. static int print_cpuinfo(void)
  165. {
  166. struct udevice *dev;
  167. char desc[512];
  168. int ret;
  169. dev = cpu_get_current_dev();
  170. if (!dev) {
  171. debug("%s: Could not get CPU device\n",
  172. __func__);
  173. return -ENODEV;
  174. }
  175. ret = cpu_get_desc(dev, desc, sizeof(desc));
  176. if (ret) {
  177. debug("%s: Could not get CPU description (err = %d)\n",
  178. dev->name, ret);
  179. return ret;
  180. }
  181. printf("CPU: %s\n", desc);
  182. return 0;
  183. }
  184. #endif
  185. static int announce_dram_init(void)
  186. {
  187. puts("DRAM: ");
  188. return 0;
  189. }
  190. static int show_dram_config(void)
  191. {
  192. unsigned long long size;
  193. int i;
  194. debug("\nRAM Configuration:\n");
  195. for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  196. size += gd->bd->bi_dram[i].size;
  197. debug("Bank #%d: %llx ", i,
  198. (unsigned long long)(gd->bd->bi_dram[i].start));
  199. #ifdef DEBUG
  200. print_size(gd->bd->bi_dram[i].size, "\n");
  201. #endif
  202. }
  203. debug("\nDRAM: ");
  204. print_size(size, "");
  205. board_add_ram_info(0);
  206. putc('\n');
  207. return 0;
  208. }
  209. __weak int dram_init_banksize(void)
  210. {
  211. gd->bd->bi_dram[0].start = gd->ram_base;
  212. gd->bd->bi_dram[0].size = get_effective_memsize();
  213. return 0;
  214. }
  215. #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
  216. static int init_func_i2c(void)
  217. {
  218. puts("I2C: ");
  219. i2c_init_all();
  220. puts("ready\n");
  221. return 0;
  222. }
  223. #endif
  224. #if defined(CONFIG_VID)
  225. __weak int init_func_vid(void)
  226. {
  227. return 0;
  228. }
  229. #endif
  230. static int setup_mon_len(void)
  231. {
  232. #if defined(__ARM__) || defined(__MICROBLAZE__)
  233. gd->mon_len = (ulong)&__bss_end - (ulong)_start;
  234. #elif defined(CONFIG_SANDBOX)
  235. gd->mon_len = 0;
  236. #elif defined(CONFIG_EFI_APP)
  237. gd->mon_len = (ulong)&_end - (ulong)_init;
  238. #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
  239. gd->mon_len = CONFIG_SYS_MONITOR_LEN;
  240. #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
  241. gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
  242. #elif defined(CONFIG_SYS_MONITOR_BASE)
  243. /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
  244. gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
  245. #endif
  246. return 0;
  247. }
  248. static int setup_spl_handoff(void)
  249. {
  250. #if CONFIG_IS_ENABLED(HANDOFF)
  251. gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
  252. sizeof(struct spl_handoff));
  253. debug("Found SPL hand-off info %p\n", gd->spl_handoff);
  254. #endif
  255. return 0;
  256. }
  257. __weak int arch_cpu_init(void)
  258. {
  259. return 0;
  260. }
  261. __weak int mach_cpu_init(void)
  262. {
  263. return 0;
  264. }
  265. /* Get the top of usable RAM */
  266. __weak ulong board_get_usable_ram_top(ulong total_size)
  267. {
  268. #if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0
  269. /*
  270. * Detect whether we have so much RAM that it goes past the end of our
  271. * 32-bit address space. If so, clip the usable RAM so it doesn't.
  272. */
  273. if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
  274. /*
  275. * Will wrap back to top of 32-bit space when reservations
  276. * are made.
  277. */
  278. return 0;
  279. #endif
  280. return gd->ram_top;
  281. }
  282. static int setup_dest_addr(void)
  283. {
  284. debug("Monitor len: %08lX\n", gd->mon_len);
  285. /*
  286. * Ram is setup, size stored in gd !!
  287. */
  288. debug("Ram size: %08lX\n", (ulong)gd->ram_size);
  289. #if defined(CONFIG_SYS_MEM_TOP_HIDE)
  290. /*
  291. * Subtract specified amount of memory to hide so that it won't
  292. * get "touched" at all by U-Boot. By fixing up gd->ram_size
  293. * the Linux kernel should now get passed the now "corrected"
  294. * memory size and won't touch it either. This should work
  295. * for arch/ppc and arch/powerpc. Only Linux board ports in
  296. * arch/powerpc with bootwrapper support, that recalculate the
  297. * memory size from the SDRAM controller setup will have to
  298. * get fixed.
  299. */
  300. gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
  301. #endif
  302. #ifdef CONFIG_SYS_SDRAM_BASE
  303. gd->ram_base = CONFIG_SYS_SDRAM_BASE;
  304. #endif
  305. gd->ram_top = gd->ram_base + get_effective_memsize();
  306. gd->ram_top = board_get_usable_ram_top(gd->mon_len);
  307. gd->relocaddr = gd->ram_top;
  308. debug("Ram top: %08lX\n", (ulong)gd->ram_top);
  309. #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
  310. /*
  311. * We need to make sure the location we intend to put secondary core
  312. * boot code is reserved and not used by any part of u-boot
  313. */
  314. if (gd->relocaddr > determine_mp_bootpg(NULL)) {
  315. gd->relocaddr = determine_mp_bootpg(NULL);
  316. debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
  317. }
  318. #endif
  319. return 0;
  320. }
  321. #ifdef CONFIG_PRAM
  322. /* reserve protected RAM */
  323. static int reserve_pram(void)
  324. {
  325. ulong reg;
  326. reg = env_get_ulong("pram", 10, CONFIG_PRAM);
  327. gd->relocaddr -= (reg << 10); /* size is in kB */
  328. debug("Reserving %ldk for protected RAM at %08lx\n", reg,
  329. gd->relocaddr);
  330. return 0;
  331. }
  332. #endif /* CONFIG_PRAM */
  333. /* Round memory pointer down to next 4 kB limit */
  334. static int reserve_round_4k(void)
  335. {
  336. gd->relocaddr &= ~(4096 - 1);
  337. return 0;
  338. }
  339. __weak int arch_reserve_mmu(void)
  340. {
  341. return 0;
  342. }
  343. static int reserve_video(void)
  344. {
  345. #ifdef CONFIG_DM_VIDEO
  346. ulong addr;
  347. int ret;
  348. addr = gd->relocaddr;
  349. ret = video_reserve(&addr);
  350. if (ret)
  351. return ret;
  352. debug("Reserving %luk for video at: %08lx\n",
  353. ((unsigned long)gd->relocaddr - addr) >> 10, addr);
  354. gd->relocaddr = addr;
  355. #elif defined(CONFIG_LCD)
  356. # ifdef CONFIG_FB_ADDR
  357. gd->fb_base = CONFIG_FB_ADDR;
  358. # else
  359. /* reserve memory for LCD display (always full pages) */
  360. gd->relocaddr = lcd_setmem(gd->relocaddr);
  361. gd->fb_base = gd->relocaddr;
  362. # endif /* CONFIG_FB_ADDR */
  363. #endif
  364. return 0;
  365. }
  366. static int reserve_trace(void)
  367. {
  368. #ifdef CONFIG_TRACE
  369. gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
  370. gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
  371. debug("Reserving %luk for trace data at: %08lx\n",
  372. (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
  373. #endif
  374. return 0;
  375. }
  376. static int reserve_uboot(void)
  377. {
  378. if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
  379. /*
  380. * reserve memory for U-Boot code, data & bss
  381. * round down to next 4 kB limit
  382. */
  383. gd->relocaddr -= gd->mon_len;
  384. gd->relocaddr &= ~(4096 - 1);
  385. #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
  386. /* round down to next 64 kB limit so that IVPR stays aligned */
  387. gd->relocaddr &= ~(65536 - 1);
  388. #endif
  389. debug("Reserving %ldk for U-Boot at: %08lx\n",
  390. gd->mon_len >> 10, gd->relocaddr);
  391. }
  392. gd->start_addr_sp = gd->relocaddr;
  393. return 0;
  394. }
  395. /*
  396. * reserve after start_addr_sp the requested size and make the stack pointer
  397. * 16-byte aligned, this alignment is needed for cast on the reserved memory
  398. * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
  399. * = ARMv8 Instruction Set Overview: quad word, 16 bytes
  400. */
  401. static unsigned long reserve_stack_aligned(size_t size)
  402. {
  403. return ALIGN_DOWN(gd->start_addr_sp - size, 16);
  404. }
  405. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  406. static int reserve_noncached(void)
  407. {
  408. /*
  409. * The value of gd->start_addr_sp must match the value of malloc_start
  410. * calculated in boatrd_f.c:initr_malloc(), which is passed to
  411. * board_r.c:mem_malloc_init() and then used by
  412. * cache.c:noncached_init()
  413. *
  414. * These calculations must match the code in cache.c:noncached_init()
  415. */
  416. gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
  417. MMU_SECTION_SIZE;
  418. gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
  419. MMU_SECTION_SIZE);
  420. debug("Reserving %dM for noncached_alloc() at: %08lx\n",
  421. CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
  422. return 0;
  423. }
  424. #endif
  425. /* reserve memory for malloc() area */
  426. static int reserve_malloc(void)
  427. {
  428. gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN);
  429. debug("Reserving %dk for malloc() at: %08lx\n",
  430. TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
  431. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  432. reserve_noncached();
  433. #endif
  434. return 0;
  435. }
  436. /* (permanently) allocate a Board Info struct */
  437. static int reserve_board(void)
  438. {
  439. if (!gd->bd) {
  440. gd->start_addr_sp = reserve_stack_aligned(sizeof(struct bd_info));
  441. gd->bd = (struct bd_info *)map_sysmem(gd->start_addr_sp,
  442. sizeof(struct bd_info));
  443. memset(gd->bd, '\0', sizeof(struct bd_info));
  444. debug("Reserving %zu Bytes for Board Info at: %08lx\n",
  445. sizeof(struct bd_info), gd->start_addr_sp);
  446. }
  447. return 0;
  448. }
  449. static int reserve_global_data(void)
  450. {
  451. gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t));
  452. gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
  453. debug("Reserving %zu Bytes for Global Data at: %08lx\n",
  454. sizeof(gd_t), gd->start_addr_sp);
  455. return 0;
  456. }
  457. static int reserve_fdt(void)
  458. {
  459. if (!IS_ENABLED(CONFIG_OF_EMBED)) {
  460. /*
  461. * If the device tree is sitting immediately above our image
  462. * then we must relocate it. If it is embedded in the data
  463. * section, then it will be relocated with other data.
  464. */
  465. if (gd->fdt_blob) {
  466. gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32);
  467. gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
  468. gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
  469. debug("Reserving %lu Bytes for FDT at: %08lx\n",
  470. gd->fdt_size, gd->start_addr_sp);
  471. }
  472. }
  473. return 0;
  474. }
  475. static int reserve_bootstage(void)
  476. {
  477. #ifdef CONFIG_BOOTSTAGE
  478. int size = bootstage_get_size();
  479. gd->start_addr_sp = reserve_stack_aligned(size);
  480. gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
  481. debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
  482. gd->start_addr_sp);
  483. #endif
  484. return 0;
  485. }
  486. __weak int arch_reserve_stacks(void)
  487. {
  488. return 0;
  489. }
  490. static int reserve_stacks(void)
  491. {
  492. /* make stack pointer 16-byte aligned */
  493. gd->start_addr_sp = reserve_stack_aligned(16);
  494. /*
  495. * let the architecture-specific code tailor gd->start_addr_sp and
  496. * gd->irq_sp
  497. */
  498. return arch_reserve_stacks();
  499. }
  500. static int reserve_bloblist(void)
  501. {
  502. #ifdef CONFIG_BLOBLIST
  503. /* Align to a 4KB boundary for easier reading of addresses */
  504. gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp -
  505. CONFIG_BLOBLIST_SIZE_RELOC, 0x1000);
  506. gd->new_bloblist = map_sysmem(gd->start_addr_sp,
  507. CONFIG_BLOBLIST_SIZE_RELOC);
  508. #endif
  509. return 0;
  510. }
  511. static int display_new_sp(void)
  512. {
  513. debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
  514. return 0;
  515. }
  516. __weak int arch_setup_bdinfo(void)
  517. {
  518. return 0;
  519. }
  520. int setup_bdinfo(void)
  521. {
  522. struct bd_info *bd = gd->bd;
  523. if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
  524. bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
  525. bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
  526. }
  527. #ifdef CONFIG_MACH_TYPE
  528. bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
  529. #endif
  530. return arch_setup_bdinfo();
  531. }
  532. #ifdef CONFIG_POST
  533. static int init_post(void)
  534. {
  535. post_bootmode_init();
  536. post_run(NULL, POST_ROM | post_bootmode_get(0));
  537. return 0;
  538. }
  539. #endif
  540. static int reloc_fdt(void)
  541. {
  542. if (!IS_ENABLED(CONFIG_OF_EMBED)) {
  543. if (gd->flags & GD_FLG_SKIP_RELOC)
  544. return 0;
  545. if (gd->new_fdt) {
  546. memcpy(gd->new_fdt, gd->fdt_blob,
  547. fdt_totalsize(gd->fdt_blob));
  548. gd->fdt_blob = gd->new_fdt;
  549. }
  550. }
  551. return 0;
  552. }
  553. static int reloc_bootstage(void)
  554. {
  555. #ifdef CONFIG_BOOTSTAGE
  556. if (gd->flags & GD_FLG_SKIP_RELOC)
  557. return 0;
  558. if (gd->new_bootstage) {
  559. int size = bootstage_get_size();
  560. debug("Copying bootstage from %p to %p, size %x\n",
  561. gd->bootstage, gd->new_bootstage, size);
  562. memcpy(gd->new_bootstage, gd->bootstage, size);
  563. gd->bootstage = gd->new_bootstage;
  564. bootstage_relocate();
  565. }
  566. #endif
  567. return 0;
  568. }
  569. static int reloc_bloblist(void)
  570. {
  571. #ifdef CONFIG_BLOBLIST
  572. /*
  573. * Relocate only if we are supposed to send it
  574. */
  575. if ((gd->flags & GD_FLG_SKIP_RELOC) &&
  576. CONFIG_BLOBLIST_SIZE == CONFIG_BLOBLIST_SIZE_RELOC) {
  577. debug("Not relocating bloblist\n");
  578. return 0;
  579. }
  580. if (gd->new_bloblist) {
  581. int size = CONFIG_BLOBLIST_SIZE;
  582. debug("Copying bloblist from %p to %p, size %x\n",
  583. gd->bloblist, gd->new_bloblist, size);
  584. bloblist_reloc(gd->new_bloblist, CONFIG_BLOBLIST_SIZE_RELOC,
  585. gd->bloblist, size);
  586. gd->bloblist = gd->new_bloblist;
  587. }
  588. #endif
  589. return 0;
  590. }
  591. static int setup_reloc(void)
  592. {
  593. if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
  594. #ifdef CONFIG_SYS_TEXT_BASE
  595. #ifdef ARM
  596. gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
  597. #elif defined(CONFIG_M68K)
  598. /*
  599. * On all ColdFire arch cpu, monitor code starts always
  600. * just after the default vector table location, so at 0x400
  601. */
  602. gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
  603. #elif !defined(CONFIG_SANDBOX)
  604. gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
  605. #endif
  606. #endif
  607. }
  608. memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
  609. if (gd->flags & GD_FLG_SKIP_RELOC) {
  610. debug("Skipping relocation due to flag\n");
  611. } else {
  612. debug("Relocation Offset is: %08lx\n", gd->reloc_off);
  613. debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
  614. gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
  615. gd->start_addr_sp);
  616. }
  617. return 0;
  618. }
  619. #ifdef CONFIG_OF_BOARD_FIXUP
  620. static int fix_fdt(void)
  621. {
  622. return board_fix_fdt((void *)gd->fdt_blob);
  623. }
  624. #endif
  625. /* ARM calls relocate_code from its crt0.S */
  626. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  627. !CONFIG_IS_ENABLED(X86_64)
  628. static int jump_to_copy(void)
  629. {
  630. if (gd->flags & GD_FLG_SKIP_RELOC)
  631. return 0;
  632. /*
  633. * x86 is special, but in a nice way. It uses a trampoline which
  634. * enables the dcache if possible.
  635. *
  636. * For now, other archs use relocate_code(), which is implemented
  637. * similarly for all archs. When we do generic relocation, hopefully
  638. * we can make all archs enable the dcache prior to relocation.
  639. */
  640. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  641. /*
  642. * SDRAM and console are now initialised. The final stack can now
  643. * be setup in SDRAM. Code execution will continue in Flash, but
  644. * with the stack in SDRAM and Global Data in temporary memory
  645. * (CPU cache)
  646. */
  647. arch_setup_gd(gd->new_gd);
  648. board_init_f_r_trampoline(gd->start_addr_sp);
  649. #else
  650. relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
  651. #endif
  652. return 0;
  653. }
  654. #endif
  655. /* Record the board_init_f() bootstage (after arch_cpu_init()) */
  656. static int initf_bootstage(void)
  657. {
  658. bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
  659. IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
  660. int ret;
  661. ret = bootstage_init(!from_spl);
  662. if (ret)
  663. return ret;
  664. if (from_spl) {
  665. const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
  666. CONFIG_BOOTSTAGE_STASH_SIZE);
  667. ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
  668. if (ret && ret != -ENOENT) {
  669. debug("Failed to unstash bootstage: err=%d\n", ret);
  670. return ret;
  671. }
  672. }
  673. bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
  674. return 0;
  675. }
  676. static int initf_dm(void)
  677. {
  678. #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  679. int ret;
  680. bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f");
  681. ret = dm_init_and_scan(true);
  682. bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F);
  683. if (ret)
  684. return ret;
  685. if (IS_ENABLED(CONFIG_TIMER_EARLY)) {
  686. ret = dm_timer_init();
  687. if (ret)
  688. return ret;
  689. }
  690. #endif
  691. return 0;
  692. }
  693. /* Architecture-specific memory reservation */
  694. __weak int reserve_arch(void)
  695. {
  696. return 0;
  697. }
  698. __weak int arch_cpu_init_dm(void)
  699. {
  700. return 0;
  701. }
  702. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_JH7100)
  703. extern int board_hw_init(void);
  704. #endif
  705. __weak int checkcpu(void)
  706. {
  707. return 0;
  708. }
  709. __weak int clear_bss(void)
  710. {
  711. return 0;
  712. }
  713. static const init_fnc_t init_sequence_f[] = {
  714. setup_mon_len,
  715. #ifdef CONFIG_OF_CONTROL
  716. fdtdec_setup,
  717. #endif
  718. #ifdef CONFIG_TRACE_EARLY
  719. trace_early_init,
  720. #endif
  721. initf_malloc,
  722. log_init,
  723. initf_bootstage, /* uses its own timer, so does not need DM */
  724. #ifdef CONFIG_BLOBLIST
  725. bloblist_init,
  726. #endif
  727. setup_spl_handoff,
  728. #if defined(CONFIG_CONSOLE_RECORD_INIT_F)
  729. console_record_init,
  730. #endif
  731. #if defined(CONFIG_HAVE_FSP)
  732. arch_fsp_init,
  733. #endif
  734. arch_cpu_init, /* basic arch cpu dependent setup */
  735. mach_cpu_init, /* SoC/machine dependent CPU setup */
  736. initf_dm,
  737. arch_cpu_init_dm,
  738. #if defined(CONFIG_BOARD_EARLY_INIT_F)
  739. board_early_init_f,
  740. #endif
  741. #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
  742. /* get CPU and bus clocks according to the environment variable */
  743. get_clocks, /* get CPU and bus clocks (etc.) */
  744. #endif
  745. #if !defined(CONFIG_M68K)
  746. timer_init, /* initialize timer */
  747. #endif
  748. #if defined(CONFIG_BOARD_POSTCLK_INIT)
  749. board_postclk_init,
  750. #endif
  751. env_init, /* initialize environment */
  752. init_baud_rate, /* initialze baudrate settings */
  753. serial_init, /* serial communications setup */
  754. console_init_f, /* stage 1 init of console */
  755. display_options, /* say that we are here */
  756. display_text_info, /* show debugging info if required */
  757. checkcpu,
  758. #if defined(CONFIG_SYSRESET)
  759. print_resetinfo,
  760. #endif
  761. #if defined(CONFIG_DISPLAY_CPUINFO)
  762. print_cpuinfo, /* display cpu info (and speed) */
  763. #endif
  764. #if defined(CONFIG_DTB_RESELECT)
  765. embedded_dtb_select,
  766. #endif
  767. #if defined(CONFIG_DISPLAY_BOARDINFO)
  768. show_board_info,
  769. #endif
  770. INIT_FUNC_WATCHDOG_INIT
  771. #if defined(CONFIG_MISC_INIT_F)
  772. misc_init_f,
  773. #endif
  774. INIT_FUNC_WATCHDOG_RESET
  775. #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
  776. init_func_i2c,
  777. #endif
  778. #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
  779. init_func_vid,
  780. #endif
  781. announce_dram_init,
  782. dram_init, /* configure available RAM banks */
  783. #ifdef CONFIG_POST
  784. post_init_f,
  785. #endif
  786. INIT_FUNC_WATCHDOG_RESET
  787. #if defined(CONFIG_SYS_DRAM_TEST)
  788. testdram,
  789. #endif /* CONFIG_SYS_DRAM_TEST */
  790. INIT_FUNC_WATCHDOG_RESET
  791. #ifdef CONFIG_POST
  792. init_post,
  793. #endif
  794. INIT_FUNC_WATCHDOG_RESET
  795. /*
  796. * Now that we have DRAM mapped and working, we can
  797. * relocate the code and continue running from DRAM.
  798. *
  799. * Reserve memory at end of RAM for (top down in that order):
  800. * - area that won't get touched by U-Boot and Linux (optional)
  801. * - kernel log buffer
  802. * - protected RAM
  803. * - LCD framebuffer
  804. * - monitor code
  805. * - board info struct
  806. */
  807. setup_dest_addr,
  808. #ifdef CONFIG_OF_BOARD_FIXUP
  809. fix_fdt,
  810. #endif
  811. #ifdef CONFIG_PRAM
  812. reserve_pram,
  813. #endif
  814. reserve_round_4k,
  815. arch_reserve_mmu,
  816. reserve_video,
  817. reserve_trace,
  818. reserve_uboot,
  819. reserve_malloc,
  820. reserve_board,
  821. reserve_global_data,
  822. reserve_fdt,
  823. reserve_bootstage,
  824. reserve_bloblist,
  825. reserve_arch,
  826. reserve_stacks,
  827. dram_init_banksize,
  828. show_dram_config,
  829. INIT_FUNC_WATCHDOG_RESET
  830. setup_bdinfo,
  831. display_new_sp,
  832. INIT_FUNC_WATCHDOG_RESET
  833. reloc_fdt,
  834. reloc_bootstage,
  835. reloc_bloblist,
  836. setup_reloc,
  837. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  838. copy_uboot_to_ram,
  839. do_elf_reloc_fixups,
  840. #endif
  841. clear_bss,
  842. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_JH7100)
  843. board_hw_init,
  844. #endif
  845. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  846. !CONFIG_IS_ENABLED(X86_64)
  847. jump_to_copy,
  848. #endif
  849. NULL,
  850. };
  851. void board_init_f(ulong boot_flags)
  852. {
  853. gd->flags = boot_flags;
  854. gd->have_console = 0;
  855. if (initcall_run_list(init_sequence_f))
  856. hang();
  857. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  858. !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
  859. !defined(CONFIG_ARC)
  860. /* NOTREACHED - jump_to_copy() does not return */
  861. hang();
  862. #endif
  863. }
  864. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  865. /*
  866. * For now this code is only used on x86.
  867. *
  868. * init_sequence_f_r is the list of init functions which are run when
  869. * U-Boot is executing from Flash with a semi-limited 'C' environment.
  870. * The following limitations must be considered when implementing an
  871. * '_f_r' function:
  872. * - 'static' variables are read-only
  873. * - Global Data (gd->xxx) is read/write
  874. *
  875. * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
  876. * supported). It _should_, if possible, copy global data to RAM and
  877. * initialise the CPU caches (to speed up the relocation process)
  878. *
  879. * NOTE: At present only x86 uses this route, but it is intended that
  880. * all archs will move to this when generic relocation is implemented.
  881. */
  882. static const init_fnc_t init_sequence_f_r[] = {
  883. #if !CONFIG_IS_ENABLED(X86_64)
  884. init_cache_f_r,
  885. #endif
  886. NULL,
  887. };
  888. void board_init_f_r(void)
  889. {
  890. if (initcall_run_list(init_sequence_f_r))
  891. hang();
  892. /*
  893. * The pre-relocation drivers may be using memory that has now gone
  894. * away. Mark serial as unavailable - this will fall back to the debug
  895. * UART if available.
  896. *
  897. * Do the same with log drivers since the memory may not be available.
  898. */
  899. gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
  900. #ifdef CONFIG_TIMER
  901. gd->timer = NULL;
  902. #endif
  903. /*
  904. * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
  905. * Transfer execution from Flash to RAM by calculating the address
  906. * of the in-RAM copy of board_init_r() and calling it
  907. */
  908. (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
  909. /* NOTREACHED - board_init_r() does not return */
  910. hang();
  911. }
  912. #endif /* CONFIG_X86 */