stm32-fmc2-ebi.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) STMicroelectronics 2020
  4. */
  5. #define LOG_CATEGORY UCLASS_NOP
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <reset.h>
  10. #include <dm/device_compat.h>
  11. #include <linux/bitfield.h>
  12. #include <linux/err.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/ioport.h>
  15. /* FMC2 Controller Registers */
  16. #define FMC2_BCR1 0x0
  17. #define FMC2_BTR1 0x4
  18. #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1)
  19. #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
  20. #define FMC2_PCSCNTR 0x20
  21. #define FMC2_BWTR1 0x104
  22. #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
  23. /* Register: FMC2_BCR1 */
  24. #define FMC2_BCR1_CCLKEN BIT(20)
  25. #define FMC2_BCR1_FMC2EN BIT(31)
  26. /* Register: FMC2_BCRx */
  27. #define FMC2_BCR_MBKEN BIT(0)
  28. #define FMC2_BCR_MUXEN BIT(1)
  29. #define FMC2_BCR_MTYP GENMASK(3, 2)
  30. #define FMC2_BCR_MWID GENMASK(5, 4)
  31. #define FMC2_BCR_FACCEN BIT(6)
  32. #define FMC2_BCR_BURSTEN BIT(8)
  33. #define FMC2_BCR_WAITPOL BIT(9)
  34. #define FMC2_BCR_WAITCFG BIT(11)
  35. #define FMC2_BCR_WREN BIT(12)
  36. #define FMC2_BCR_WAITEN BIT(13)
  37. #define FMC2_BCR_EXTMOD BIT(14)
  38. #define FMC2_BCR_ASYNCWAIT BIT(15)
  39. #define FMC2_BCR_CPSIZE GENMASK(18, 16)
  40. #define FMC2_BCR_CBURSTRW BIT(19)
  41. #define FMC2_BCR_NBLSET GENMASK(23, 22)
  42. /* Register: FMC2_BTRx/FMC2_BWTRx */
  43. #define FMC2_BXTR_ADDSET GENMASK(3, 0)
  44. #define FMC2_BXTR_ADDHLD GENMASK(7, 4)
  45. #define FMC2_BXTR_DATAST GENMASK(15, 8)
  46. #define FMC2_BXTR_BUSTURN GENMASK(19, 16)
  47. #define FMC2_BTR_CLKDIV GENMASK(23, 20)
  48. #define FMC2_BTR_DATLAT GENMASK(27, 24)
  49. #define FMC2_BXTR_ACCMOD GENMASK(29, 28)
  50. #define FMC2_BXTR_DATAHLD GENMASK(31, 30)
  51. /* Register: FMC2_PCSCNTR */
  52. #define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0)
  53. #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16)
  54. #define FMC2_MAX_EBI_CE 4
  55. #define FMC2_MAX_BANKS 5
  56. #define FMC2_BCR_CPSIZE_0 0x0
  57. #define FMC2_BCR_CPSIZE_128 0x1
  58. #define FMC2_BCR_CPSIZE_256 0x2
  59. #define FMC2_BCR_CPSIZE_512 0x3
  60. #define FMC2_BCR_CPSIZE_1024 0x4
  61. #define FMC2_BCR_MWID_8 0x0
  62. #define FMC2_BCR_MWID_16 0x1
  63. #define FMC2_BCR_MTYP_SRAM 0x0
  64. #define FMC2_BCR_MTYP_PSRAM 0x1
  65. #define FMC2_BCR_MTYP_NOR 0x2
  66. #define FMC2_BXTR_EXTMOD_A 0x0
  67. #define FMC2_BXTR_EXTMOD_B 0x1
  68. #define FMC2_BXTR_EXTMOD_C 0x2
  69. #define FMC2_BXTR_EXTMOD_D 0x3
  70. #define FMC2_BCR_NBLSET_MAX 0x3
  71. #define FMC2_BXTR_ADDSET_MAX 0xf
  72. #define FMC2_BXTR_ADDHLD_MAX 0xf
  73. #define FMC2_BXTR_DATAST_MAX 0xff
  74. #define FMC2_BXTR_BUSTURN_MAX 0xf
  75. #define FMC2_BXTR_DATAHLD_MAX 0x3
  76. #define FMC2_BTR_CLKDIV_MAX 0xf
  77. #define FMC2_BTR_DATLAT_MAX 0xf
  78. #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff
  79. #define FMC2_NSEC_PER_SEC 1000000000L
  80. enum stm32_fmc2_ebi_bank {
  81. FMC2_EBI1 = 0,
  82. FMC2_EBI2,
  83. FMC2_EBI3,
  84. FMC2_EBI4,
  85. FMC2_NAND
  86. };
  87. enum stm32_fmc2_ebi_register_type {
  88. FMC2_REG_BCR = 1,
  89. FMC2_REG_BTR,
  90. FMC2_REG_BWTR,
  91. FMC2_REG_PCSCNTR
  92. };
  93. enum stm32_fmc2_ebi_transaction_type {
  94. FMC2_ASYNC_MODE_1_SRAM = 0,
  95. FMC2_ASYNC_MODE_1_PSRAM,
  96. FMC2_ASYNC_MODE_A_SRAM,
  97. FMC2_ASYNC_MODE_A_PSRAM,
  98. FMC2_ASYNC_MODE_2_NOR,
  99. FMC2_ASYNC_MODE_B_NOR,
  100. FMC2_ASYNC_MODE_C_NOR,
  101. FMC2_ASYNC_MODE_D_NOR,
  102. FMC2_SYNC_READ_SYNC_WRITE_PSRAM,
  103. FMC2_SYNC_READ_ASYNC_WRITE_PSRAM,
  104. FMC2_SYNC_READ_SYNC_WRITE_NOR,
  105. FMC2_SYNC_READ_ASYNC_WRITE_NOR
  106. };
  107. enum stm32_fmc2_ebi_buswidth {
  108. FMC2_BUSWIDTH_8 = 8,
  109. FMC2_BUSWIDTH_16 = 16
  110. };
  111. enum stm32_fmc2_ebi_cpsize {
  112. FMC2_CPSIZE_0 = 0,
  113. FMC2_CPSIZE_128 = 128,
  114. FMC2_CPSIZE_256 = 256,
  115. FMC2_CPSIZE_512 = 512,
  116. FMC2_CPSIZE_1024 = 1024
  117. };
  118. struct stm32_fmc2_ebi {
  119. struct clk clk;
  120. fdt_addr_t io_base;
  121. u8 bank_assigned;
  122. };
  123. /*
  124. * struct stm32_fmc2_prop - STM32 FMC2 EBI property
  125. * @name: the device tree binding name of the property
  126. * @bprop: indicate that it is a boolean property
  127. * @mprop: indicate that it is a mandatory property
  128. * @reg_type: the register that have to be modified
  129. * @reg_mask: the bit that have to be modified in the selected register
  130. * in case of it is a boolean property
  131. * @reset_val: the default value that have to be set in case the property
  132. * has not been defined in the device tree
  133. * @check: this callback ckecks that the property is compliant with the
  134. * transaction type selected
  135. * @calculate: this callback is called to calculate for exemple a timing
  136. * set in nanoseconds in the device tree in clock cycles or in
  137. * clock period
  138. * @set: this callback applies the values in the registers
  139. */
  140. struct stm32_fmc2_prop {
  141. const char *name;
  142. bool bprop;
  143. bool mprop;
  144. int reg_type;
  145. u32 reg_mask;
  146. u32 reset_val;
  147. int (*check)(struct stm32_fmc2_ebi *ebi,
  148. const struct stm32_fmc2_prop *prop, int cs);
  149. u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
  150. int (*set)(struct stm32_fmc2_ebi *ebi,
  151. const struct stm32_fmc2_prop *prop,
  152. int cs, u32 setup);
  153. };
  154. static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi,
  155. const struct stm32_fmc2_prop *prop,
  156. int cs)
  157. {
  158. u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
  159. if (bcr & FMC2_BCR_MTYP)
  160. return 0;
  161. return -EINVAL;
  162. }
  163. static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi,
  164. const struct stm32_fmc2_prop *prop,
  165. int cs)
  166. {
  167. u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
  168. u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  169. if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
  170. return 0;
  171. return -EINVAL;
  172. }
  173. static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi,
  174. const struct stm32_fmc2_prop *prop,
  175. int cs)
  176. {
  177. u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
  178. if (bcr & FMC2_BCR_BURSTEN)
  179. return 0;
  180. return -EINVAL;
  181. }
  182. static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
  183. const struct stm32_fmc2_prop *prop,
  184. int cs)
  185. {
  186. u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
  187. if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW))
  188. return 0;
  189. return -EINVAL;
  190. }
  191. static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi,
  192. const struct stm32_fmc2_prop *prop,
  193. int cs)
  194. {
  195. u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
  196. u32 val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
  197. if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
  198. return 0;
  199. return -EINVAL;
  200. }
  201. static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi,
  202. const struct stm32_fmc2_prop *prop,
  203. int cs)
  204. {
  205. u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
  206. u32 bxtr = prop->reg_type == FMC2_REG_BWTR ?
  207. readl(ebi->io_base + FMC2_BWTR(cs)) :
  208. readl(ebi->io_base + FMC2_BTR(cs));
  209. u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
  210. if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) &&
  211. ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN))
  212. return 0;
  213. return -EINVAL;
  214. }
  215. static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi,
  216. const struct stm32_fmc2_prop *prop,
  217. int cs)
  218. {
  219. u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
  220. u32 bcr1 = cs ? readl(ebi->io_base + FMC2_BCR1) : bcr;
  221. if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN)))
  222. return 0;
  223. return -EINVAL;
  224. }
  225. static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi,
  226. const struct stm32_fmc2_prop *prop,
  227. int cs)
  228. {
  229. if (cs)
  230. return -EINVAL;
  231. return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
  232. }
  233. static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
  234. int cs, u32 setup)
  235. {
  236. unsigned long hclk = clk_get_rate(&ebi->clk);
  237. unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
  238. return DIV_ROUND_UP(setup * 1000, hclkp);
  239. }
  240. static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
  241. int cs, u32 setup)
  242. {
  243. u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
  244. u32 bcr = readl(ebi->io_base + FMC2_BCR1);
  245. u32 btr = bcr & FMC2_BCR1_CCLKEN || !cs ?
  246. readl(ebi->io_base + FMC2_BTR1) :
  247. readl(ebi->io_base + FMC2_BTR(cs));
  248. u32 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
  249. return DIV_ROUND_UP(nb_clk_cycles, clk_period);
  250. }
  251. static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
  252. {
  253. switch (reg_type) {
  254. case FMC2_REG_BCR:
  255. *reg = FMC2_BCR(cs);
  256. break;
  257. case FMC2_REG_BTR:
  258. *reg = FMC2_BTR(cs);
  259. break;
  260. case FMC2_REG_BWTR:
  261. *reg = FMC2_BWTR(cs);
  262. break;
  263. case FMC2_REG_PCSCNTR:
  264. *reg = FMC2_PCSCNTR;
  265. break;
  266. default:
  267. return -EINVAL;
  268. }
  269. return 0;
  270. }
  271. static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi,
  272. const struct stm32_fmc2_prop *prop,
  273. int cs, u32 setup)
  274. {
  275. u32 reg;
  276. int ret;
  277. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  278. if (ret)
  279. return ret;
  280. clrsetbits_le32(ebi->io_base + reg, prop->reg_mask,
  281. setup ? prop->reg_mask : 0);
  282. return 0;
  283. }
  284. static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi,
  285. const struct stm32_fmc2_prop *prop,
  286. int cs, u32 setup)
  287. {
  288. u32 bcr_mask, bcr = FMC2_BCR_WREN;
  289. u32 btr_mask, btr = 0;
  290. u32 bwtr_mask, bwtr = 0;
  291. bwtr_mask = FMC2_BXTR_ACCMOD;
  292. btr_mask = FMC2_BXTR_ACCMOD;
  293. bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN |
  294. FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN |
  295. FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW;
  296. switch (setup) {
  297. case FMC2_ASYNC_MODE_1_SRAM:
  298. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
  299. /*
  300. * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
  301. * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
  302. */
  303. break;
  304. case FMC2_ASYNC_MODE_1_PSRAM:
  305. /*
  306. * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
  307. * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
  308. */
  309. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
  310. break;
  311. case FMC2_ASYNC_MODE_A_SRAM:
  312. /*
  313. * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
  314. * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
  315. */
  316. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
  317. bcr |= FMC2_BCR_EXTMOD;
  318. btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
  319. bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
  320. break;
  321. case FMC2_ASYNC_MODE_A_PSRAM:
  322. /*
  323. * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
  324. * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
  325. */
  326. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
  327. bcr |= FMC2_BCR_EXTMOD;
  328. btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
  329. bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
  330. break;
  331. case FMC2_ASYNC_MODE_2_NOR:
  332. /*
  333. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
  334. * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
  335. */
  336. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  337. bcr |= FMC2_BCR_FACCEN;
  338. break;
  339. case FMC2_ASYNC_MODE_B_NOR:
  340. /*
  341. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
  342. * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1
  343. */
  344. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  345. bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
  346. btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
  347. bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
  348. break;
  349. case FMC2_ASYNC_MODE_C_NOR:
  350. /*
  351. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
  352. * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2
  353. */
  354. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  355. bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
  356. btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
  357. bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
  358. break;
  359. case FMC2_ASYNC_MODE_D_NOR:
  360. /*
  361. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
  362. * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3
  363. */
  364. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  365. bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
  366. btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
  367. bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
  368. break;
  369. case FMC2_SYNC_READ_SYNC_WRITE_PSRAM:
  370. /*
  371. * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
  372. * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
  373. */
  374. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
  375. bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
  376. break;
  377. case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM:
  378. /*
  379. * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
  380. * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
  381. */
  382. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
  383. bcr |= FMC2_BCR_BURSTEN;
  384. break;
  385. case FMC2_SYNC_READ_SYNC_WRITE_NOR:
  386. /*
  387. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
  388. * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
  389. */
  390. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  391. bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
  392. break;
  393. case FMC2_SYNC_READ_ASYNC_WRITE_NOR:
  394. /*
  395. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
  396. * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
  397. */
  398. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  399. bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN;
  400. break;
  401. default:
  402. /* Type of transaction not supported */
  403. return -EINVAL;
  404. }
  405. if (bcr & FMC2_BCR_EXTMOD)
  406. clrsetbits_le32(ebi->io_base + FMC2_BWTR(cs),
  407. bwtr_mask, bwtr);
  408. clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), btr_mask, btr);
  409. clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), bcr_mask, bcr);
  410. return 0;
  411. }
  412. static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi,
  413. const struct stm32_fmc2_prop *prop,
  414. int cs, u32 setup)
  415. {
  416. u32 val;
  417. switch (setup) {
  418. case FMC2_BUSWIDTH_8:
  419. val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8);
  420. break;
  421. case FMC2_BUSWIDTH_16:
  422. val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16);
  423. break;
  424. default:
  425. /* Buswidth not supported */
  426. return -EINVAL;
  427. }
  428. clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MWID, val);
  429. return 0;
  430. }
  431. static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi,
  432. const struct stm32_fmc2_prop *prop,
  433. int cs, u32 setup)
  434. {
  435. u32 val;
  436. switch (setup) {
  437. case FMC2_CPSIZE_0:
  438. val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0);
  439. break;
  440. case FMC2_CPSIZE_128:
  441. val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128);
  442. break;
  443. case FMC2_CPSIZE_256:
  444. val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256);
  445. break;
  446. case FMC2_CPSIZE_512:
  447. val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512);
  448. break;
  449. case FMC2_CPSIZE_1024:
  450. val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024);
  451. break;
  452. default:
  453. /* Cpsize not supported */
  454. return -EINVAL;
  455. }
  456. clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);
  457. return 0;
  458. }
  459. static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi,
  460. const struct stm32_fmc2_prop *prop,
  461. int cs, u32 setup)
  462. {
  463. u32 val;
  464. val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX);
  465. val = FIELD_PREP(FMC2_BCR_NBLSET, val);
  466. clrsetbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_NBLSET, val);
  467. return 0;
  468. }
  469. static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi,
  470. const struct stm32_fmc2_prop *prop,
  471. int cs, u32 setup)
  472. {
  473. u32 bcr = readl(ebi->io_base + FMC2_BCR(cs));
  474. u32 bxtr = prop->reg_type == FMC2_REG_BWTR ?
  475. readl(ebi->io_base + FMC2_BWTR(cs)) :
  476. readl(ebi->io_base + FMC2_BTR(cs));
  477. u32 reg, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
  478. int ret;
  479. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  480. if (ret)
  481. return ret;
  482. if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)
  483. val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX);
  484. else
  485. val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX);
  486. val = FIELD_PREP(FMC2_BXTR_ADDSET, val);
  487. clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDSET, val);
  488. return 0;
  489. }
  490. static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi,
  491. const struct stm32_fmc2_prop *prop,
  492. int cs, u32 setup)
  493. {
  494. u32 val, reg;
  495. int ret;
  496. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  497. if (ret)
  498. return ret;
  499. val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX);
  500. val = FIELD_PREP(FMC2_BXTR_ADDHLD, val);
  501. clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_ADDHLD, val);
  502. return 0;
  503. }
  504. static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi,
  505. const struct stm32_fmc2_prop *prop,
  506. int cs, u32 setup)
  507. {
  508. u32 val, reg;
  509. int ret;
  510. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  511. if (ret)
  512. return ret;
  513. val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX);
  514. val = FIELD_PREP(FMC2_BXTR_DATAST, val);
  515. clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAST, val);
  516. return 0;
  517. }
  518. static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi,
  519. const struct stm32_fmc2_prop *prop,
  520. int cs, u32 setup)
  521. {
  522. u32 val, reg;
  523. int ret;
  524. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  525. if (ret)
  526. return ret;
  527. val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0;
  528. val = FIELD_PREP(FMC2_BXTR_BUSTURN, val);
  529. clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_BUSTURN, val);
  530. return 0;
  531. }
  532. static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi,
  533. const struct stm32_fmc2_prop *prop,
  534. int cs, u32 setup)
  535. {
  536. u32 val, reg;
  537. int ret;
  538. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  539. if (ret)
  540. return ret;
  541. if (prop->reg_type == FMC2_REG_BWTR)
  542. val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0;
  543. else
  544. val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX);
  545. val = FIELD_PREP(FMC2_BXTR_DATAHLD, val);
  546. clrsetbits_le32(ebi->io_base + reg, FMC2_BXTR_DATAHLD, val);
  547. return 0;
  548. }
  549. static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi,
  550. const struct stm32_fmc2_prop *prop,
  551. int cs, u32 setup)
  552. {
  553. u32 val;
  554. val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1;
  555. val = FIELD_PREP(FMC2_BTR_CLKDIV, val);
  556. clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_CLKDIV, val);
  557. return 0;
  558. }
  559. static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi,
  560. const struct stm32_fmc2_prop *prop,
  561. int cs, u32 setup)
  562. {
  563. u32 val;
  564. val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0;
  565. val = FIELD_PREP(FMC2_BTR_DATLAT, val);
  566. clrsetbits_le32(ebi->io_base + FMC2_BTR(cs), FMC2_BTR_DATLAT, val);
  567. return 0;
  568. }
  569. static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi,
  570. const struct stm32_fmc2_prop *prop,
  571. int cs, u32 setup)
  572. {
  573. u32 old_val, new_val, pcscntr;
  574. if (setup < 1)
  575. return 0;
  576. pcscntr = readl(ebi->io_base + FMC2_PCSCNTR);
  577. /* Enable counter for the bank */
  578. setbits_le32(ebi->io_base + FMC2_PCSCNTR, FMC2_PCSCNTR_CNTBEN(cs));
  579. new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX);
  580. old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr);
  581. if (old_val && new_val > old_val)
  582. /* Keep current counter value */
  583. return 0;
  584. new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val);
  585. clrsetbits_le32(ebi->io_base + FMC2_PCSCNTR,
  586. FMC2_PCSCNTR_CSCOUNT, new_val);
  587. return 0;
  588. }
  589. static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = {
  590. /* st,fmc2-ebi-cs-trans-type must be the first property */
  591. {
  592. .name = "st,fmc2-ebi-cs-transaction-type",
  593. .mprop = true,
  594. .set = stm32_fmc2_ebi_set_trans_type,
  595. },
  596. {
  597. .name = "st,fmc2-ebi-cs-cclk-enable",
  598. .bprop = true,
  599. .reg_type = FMC2_REG_BCR,
  600. .reg_mask = FMC2_BCR1_CCLKEN,
  601. .check = stm32_fmc2_ebi_check_cclk,
  602. .set = stm32_fmc2_ebi_set_bit_field,
  603. },
  604. {
  605. .name = "st,fmc2-ebi-cs-mux-enable",
  606. .bprop = true,
  607. .reg_type = FMC2_REG_BCR,
  608. .reg_mask = FMC2_BCR_MUXEN,
  609. .check = stm32_fmc2_ebi_check_mux,
  610. .set = stm32_fmc2_ebi_set_bit_field,
  611. },
  612. {
  613. .name = "st,fmc2-ebi-cs-buswidth",
  614. .reset_val = FMC2_BUSWIDTH_16,
  615. .set = stm32_fmc2_ebi_set_buswidth,
  616. },
  617. {
  618. .name = "st,fmc2-ebi-cs-waitpol-high",
  619. .bprop = true,
  620. .reg_type = FMC2_REG_BCR,
  621. .reg_mask = FMC2_BCR_WAITPOL,
  622. .set = stm32_fmc2_ebi_set_bit_field,
  623. },
  624. {
  625. .name = "st,fmc2-ebi-cs-waitcfg-enable",
  626. .bprop = true,
  627. .reg_type = FMC2_REG_BCR,
  628. .reg_mask = FMC2_BCR_WAITCFG,
  629. .check = stm32_fmc2_ebi_check_waitcfg,
  630. .set = stm32_fmc2_ebi_set_bit_field,
  631. },
  632. {
  633. .name = "st,fmc2-ebi-cs-wait-enable",
  634. .bprop = true,
  635. .reg_type = FMC2_REG_BCR,
  636. .reg_mask = FMC2_BCR_WAITEN,
  637. .check = stm32_fmc2_ebi_check_sync_trans,
  638. .set = stm32_fmc2_ebi_set_bit_field,
  639. },
  640. {
  641. .name = "st,fmc2-ebi-cs-asyncwait-enable",
  642. .bprop = true,
  643. .reg_type = FMC2_REG_BCR,
  644. .reg_mask = FMC2_BCR_ASYNCWAIT,
  645. .check = stm32_fmc2_ebi_check_async_trans,
  646. .set = stm32_fmc2_ebi_set_bit_field,
  647. },
  648. {
  649. .name = "st,fmc2-ebi-cs-cpsize",
  650. .check = stm32_fmc2_ebi_check_cpsize,
  651. .set = stm32_fmc2_ebi_set_cpsize,
  652. },
  653. {
  654. .name = "st,fmc2-ebi-cs-byte-lane-setup-ns",
  655. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  656. .set = stm32_fmc2_ebi_set_bl_setup,
  657. },
  658. {
  659. .name = "st,fmc2-ebi-cs-address-setup-ns",
  660. .reg_type = FMC2_REG_BTR,
  661. .reset_val = FMC2_BXTR_ADDSET_MAX,
  662. .check = stm32_fmc2_ebi_check_async_trans,
  663. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  664. .set = stm32_fmc2_ebi_set_address_setup,
  665. },
  666. {
  667. .name = "st,fmc2-ebi-cs-address-hold-ns",
  668. .reg_type = FMC2_REG_BTR,
  669. .reset_val = FMC2_BXTR_ADDHLD_MAX,
  670. .check = stm32_fmc2_ebi_check_address_hold,
  671. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  672. .set = stm32_fmc2_ebi_set_address_hold,
  673. },
  674. {
  675. .name = "st,fmc2-ebi-cs-data-setup-ns",
  676. .reg_type = FMC2_REG_BTR,
  677. .reset_val = FMC2_BXTR_DATAST_MAX,
  678. .check = stm32_fmc2_ebi_check_async_trans,
  679. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  680. .set = stm32_fmc2_ebi_set_data_setup,
  681. },
  682. {
  683. .name = "st,fmc2-ebi-cs-bus-turnaround-ns",
  684. .reg_type = FMC2_REG_BTR,
  685. .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
  686. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  687. .set = stm32_fmc2_ebi_set_bus_turnaround,
  688. },
  689. {
  690. .name = "st,fmc2-ebi-cs-data-hold-ns",
  691. .reg_type = FMC2_REG_BTR,
  692. .check = stm32_fmc2_ebi_check_async_trans,
  693. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  694. .set = stm32_fmc2_ebi_set_data_hold,
  695. },
  696. {
  697. .name = "st,fmc2-ebi-cs-clk-period-ns",
  698. .reset_val = FMC2_BTR_CLKDIV_MAX + 1,
  699. .check = stm32_fmc2_ebi_check_clk_period,
  700. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  701. .set = stm32_fmc2_ebi_set_clk_period,
  702. },
  703. {
  704. .name = "st,fmc2-ebi-cs-data-latency-ns",
  705. .check = stm32_fmc2_ebi_check_sync_trans,
  706. .calculate = stm32_fmc2_ebi_ns_to_clk_period,
  707. .set = stm32_fmc2_ebi_set_data_latency,
  708. },
  709. {
  710. .name = "st,fmc2-ebi-cs-write-address-setup-ns",
  711. .reg_type = FMC2_REG_BWTR,
  712. .reset_val = FMC2_BXTR_ADDSET_MAX,
  713. .check = stm32_fmc2_ebi_check_async_trans,
  714. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  715. .set = stm32_fmc2_ebi_set_address_setup,
  716. },
  717. {
  718. .name = "st,fmc2-ebi-cs-write-address-hold-ns",
  719. .reg_type = FMC2_REG_BWTR,
  720. .reset_val = FMC2_BXTR_ADDHLD_MAX,
  721. .check = stm32_fmc2_ebi_check_address_hold,
  722. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  723. .set = stm32_fmc2_ebi_set_address_hold,
  724. },
  725. {
  726. .name = "st,fmc2-ebi-cs-write-data-setup-ns",
  727. .reg_type = FMC2_REG_BWTR,
  728. .reset_val = FMC2_BXTR_DATAST_MAX,
  729. .check = stm32_fmc2_ebi_check_async_trans,
  730. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  731. .set = stm32_fmc2_ebi_set_data_setup,
  732. },
  733. {
  734. .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns",
  735. .reg_type = FMC2_REG_BWTR,
  736. .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
  737. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  738. .set = stm32_fmc2_ebi_set_bus_turnaround,
  739. },
  740. {
  741. .name = "st,fmc2-ebi-cs-write-data-hold-ns",
  742. .reg_type = FMC2_REG_BWTR,
  743. .check = stm32_fmc2_ebi_check_async_trans,
  744. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  745. .set = stm32_fmc2_ebi_set_data_hold,
  746. },
  747. {
  748. .name = "st,fmc2-ebi-cs-max-low-pulse-ns",
  749. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  750. .set = stm32_fmc2_ebi_set_max_low_pulse,
  751. },
  752. };
  753. static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
  754. ofnode node,
  755. const struct stm32_fmc2_prop *prop,
  756. int cs)
  757. {
  758. u32 setup = 0;
  759. if (!prop->set) {
  760. log_err("property %s is not well defined\n", prop->name);
  761. return -EINVAL;
  762. }
  763. if (prop->check && prop->check(ebi, prop, cs))
  764. /* Skip this property */
  765. return 0;
  766. if (prop->bprop) {
  767. bool bprop;
  768. bprop = ofnode_read_bool(node, prop->name);
  769. if (prop->mprop && !bprop) {
  770. log_err("mandatory property %s not defined in the device tree\n",
  771. prop->name);
  772. return -EINVAL;
  773. }
  774. if (bprop)
  775. setup = 1;
  776. } else {
  777. u32 val;
  778. int ret;
  779. ret = ofnode_read_u32(node, prop->name, &val);
  780. if (prop->mprop && ret) {
  781. log_err("mandatory property %s not defined in the device tree\n",
  782. prop->name);
  783. return ret;
  784. }
  785. if (ret)
  786. setup = prop->reset_val;
  787. else if (prop->calculate)
  788. setup = prop->calculate(ebi, cs, val);
  789. else
  790. setup = val;
  791. }
  792. return prop->set(ebi, prop, cs, setup);
  793. }
  794. static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs)
  795. {
  796. setbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN);
  797. }
  798. static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs)
  799. {
  800. clrbits_le32(ebi->io_base + FMC2_BCR(cs), FMC2_BCR_MBKEN);
  801. }
  802. /* NWAIT signal can not be connected to EBI controller and NAND controller */
  803. static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi)
  804. {
  805. unsigned int cs;
  806. u32 bcr;
  807. for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
  808. if (!(ebi->bank_assigned & BIT(cs)))
  809. continue;
  810. bcr = readl(ebi->io_base + FMC2_BCR(cs));
  811. if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) &&
  812. ebi->bank_assigned & BIT(FMC2_NAND))
  813. return true;
  814. }
  815. return false;
  816. }
  817. static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi)
  818. {
  819. setbits_le32(ebi->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN);
  820. }
  821. static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
  822. ofnode node, u32 cs)
  823. {
  824. unsigned int i;
  825. int ret;
  826. stm32_fmc2_ebi_disable_bank(ebi, cs);
  827. for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) {
  828. const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i];
  829. ret = stm32_fmc2_ebi_parse_prop(ebi, node, p, cs);
  830. if (ret) {
  831. log_err("property %s could not be set: %d\n",
  832. p->name, ret);
  833. return ret;
  834. }
  835. }
  836. stm32_fmc2_ebi_enable_bank(ebi, cs);
  837. return 0;
  838. }
  839. static int stm32_fmc2_ebi_parse_dt(struct udevice *dev,
  840. struct stm32_fmc2_ebi *ebi)
  841. {
  842. ofnode child;
  843. bool child_found = false;
  844. u32 bank;
  845. int ret;
  846. dev_for_each_subnode(child, dev) {
  847. ret = ofnode_read_u32(child, "reg", &bank);
  848. if (ret) {
  849. dev_err(dev, "could not retrieve reg property: %d\n", ret);
  850. return ret;
  851. }
  852. if (bank >= FMC2_MAX_BANKS) {
  853. dev_err(dev, "invalid reg value: %d\n", bank);
  854. return -EINVAL;
  855. }
  856. if (ebi->bank_assigned & BIT(bank)) {
  857. dev_err(dev, "bank already assigned: %d\n", bank);
  858. return -EINVAL;
  859. }
  860. if (bank < FMC2_MAX_EBI_CE) {
  861. ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
  862. if (ret) {
  863. dev_err(dev, "setup chip select %d failed: %d\n", bank, ret);
  864. return ret;
  865. }
  866. }
  867. ebi->bank_assigned |= BIT(bank);
  868. child_found = true;
  869. }
  870. if (!child_found) {
  871. dev_warn(dev, "no subnodes found, disable the driver.\n");
  872. return -ENODEV;
  873. }
  874. if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
  875. dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
  876. return -EINVAL;
  877. }
  878. stm32_fmc2_ebi_enable(ebi);
  879. return 0;
  880. }
  881. static int stm32_fmc2_ebi_probe(struct udevice *dev)
  882. {
  883. struct stm32_fmc2_ebi *ebi = dev_get_priv(dev);
  884. struct reset_ctl reset;
  885. int ret;
  886. ebi->io_base = dev_read_addr(dev);
  887. if (ebi->io_base == FDT_ADDR_T_NONE)
  888. return -EINVAL;
  889. ret = clk_get_by_index(dev, 0, &ebi->clk);
  890. if (ret)
  891. return ret;
  892. ret = clk_enable(&ebi->clk);
  893. if (ret)
  894. return ret;
  895. ret = reset_get_by_index(dev, 0, &reset);
  896. if (!ret) {
  897. reset_assert(&reset);
  898. udelay(2);
  899. reset_deassert(&reset);
  900. }
  901. return stm32_fmc2_ebi_parse_dt(dev, ebi);
  902. }
  903. static const struct udevice_id stm32_fmc2_ebi_match[] = {
  904. {.compatible = "st,stm32mp1-fmc2-ebi"},
  905. { /* Sentinel */ }
  906. };
  907. U_BOOT_DRIVER(stm32_fmc2_ebi) = {
  908. .name = "stm32_fmc2_ebi",
  909. .id = UCLASS_NOP,
  910. .of_match = stm32_fmc2_ebi_match,
  911. .probe = stm32_fmc2_ebi_probe,
  912. .priv_auto = sizeof(struct stm32_fmc2_ebi),
  913. .bind = dm_scan_fdt_dev,
  914. };