blanche.c 7.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/blanche/blanche.c
  4. * This file is blanche board support.
  5. *
  6. * Copyright (C) 2016 Renesas Electronics Corporation
  7. */
  8. #include <common.h>
  9. #include <asm/arch/mmc.h>
  10. #include <asm/arch/rcar-mstp.h>
  11. #include <asm/arch/rmobile.h>
  12. #include <asm/arch/sh_sdhi.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <asm/mach-types.h>
  17. #include <asm/processor.h>
  18. #include <dm.h>
  19. #include <dm/platform_data/serial_sh.h>
  20. #include <env.h>
  21. #include <environment.h>
  22. #include <i2c.h>
  23. #include <linux/errno.h>
  24. #include <malloc.h>
  25. #include <miiphy.h>
  26. #include <mmc.h>
  27. #include <netdev.h>
  28. #include "qos.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #define CPG_PLL1CR 0xE6150028
  31. #define CPG_PLL3CR 0xE61500DC
  32. #define TMU0_MSTP125 BIT(25)
  33. #define QSPI_MSTP917 BIT(17)
  34. struct reg_config {
  35. u16 off;
  36. u32 val;
  37. };
  38. static void blanche_init_sys(void)
  39. {
  40. struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  41. struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  42. u32 cpu_type;
  43. cpu_type = rmobile_get_cpu_type();
  44. if (cpu_type == 0x4A) {
  45. writel(0x4D000000, CPG_PLL1CR);
  46. writel(0x4F000000, CPG_PLL3CR);
  47. }
  48. /* Watchdog init */
  49. writel(0xA5A5A500, &rwdt->rwtcsra);
  50. writel(0xA5A5A500, &swdt->swtcsra);
  51. }
  52. static void blanche_init_pfc(void)
  53. {
  54. static const struct reg_config pfc_with_unlock[] = {
  55. { 0x0004, 0x0bffffff },
  56. { 0x0008, 0x002fffff },
  57. { 0x0014, 0x00000fff },
  58. { 0x0018, 0x00010fff },
  59. { 0x001c, 0x00010fff },
  60. { 0x0020, 0x00010fff },
  61. { 0x0024, 0x00010fff },
  62. { 0x0028, 0x00010fff },
  63. { 0x002c, 0x04006000 },
  64. { 0x0030, 0x303fefe0 },
  65. { 0x0058, 0x0002000e },
  66. };
  67. static const struct reg_config pfc_without_unlock[] = {
  68. { 0x0108, 0x00000000 },
  69. { 0x010c, 0x0803FF40 },
  70. { 0x0110, 0x0000FFFF },
  71. { 0x0114, 0x00010FFF },
  72. { 0x011c, 0x0001AFFF },
  73. { 0x0124, 0x0001CFFF },
  74. { 0x0128, 0xC0438001 },
  75. { 0x012c, 0x0FC00007 },
  76. };
  77. static const u32 pfc_base = 0xe6060000;
  78. unsigned int i;
  79. for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
  80. writel(~pfc_with_unlock[i].val, pfc_base);
  81. writel(pfc_with_unlock[i].val,
  82. pfc_base | pfc_with_unlock[i].off);
  83. }
  84. for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
  85. writel(pfc_without_unlock[i].val,
  86. pfc_base | pfc_without_unlock[i].off);
  87. }
  88. static void blanche_init_lbsc(void)
  89. {
  90. static const struct reg_config lbsc_config[] = {
  91. { 0x00, 0x00000020 },
  92. { 0x08, 0x00002020 },
  93. { 0x30, 0x2a103320 },
  94. { 0x38, 0x19102110 },
  95. };
  96. static const u32 lbsc_base = 0xfec00200;
  97. unsigned int i;
  98. for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
  99. writel(lbsc_config[i].val,
  100. lbsc_base | lbsc_config[i].off);
  101. writel(lbsc_config[i].val,
  102. lbsc_base | (lbsc_config[i].off + 4));
  103. }
  104. }
  105. #if defined(CONFIG_MTD_NOR_FLASH)
  106. static void dbsc_wait(u16 reg)
  107. {
  108. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  109. while (!(readl(dbsc3_0_base + reg) & BIT(0)))
  110. ;
  111. }
  112. static void blanche_init_dbsc(void)
  113. {
  114. static const struct reg_config dbsc_config1[] = {
  115. { 0x0280, 0x0000a55a },
  116. { 0x0018, 0x21000000 },
  117. { 0x0018, 0x11000000 },
  118. { 0x0018, 0x10000000 },
  119. { 0x0290, 0x00000001 },
  120. { 0x02a0, 0x80000000 },
  121. { 0x0290, 0x00000004 },
  122. };
  123. static const struct reg_config dbsc_config2[] = {
  124. { 0x0290, 0x00000006 },
  125. { 0x02a0, 0x0001c000 },
  126. };
  127. static const struct reg_config dbsc_config4[] = {
  128. { 0x0290, 0x0000000f },
  129. { 0x02a0, 0x00181ee4 },
  130. { 0x0290, 0x00000010 },
  131. { 0x02a0, 0xf00464db },
  132. { 0x0290, 0x00000061 },
  133. { 0x02a0, 0x0000008d },
  134. { 0x0290, 0x00000001 },
  135. { 0x02a0, 0x00000073 },
  136. { 0x0020, 0x00000007 },
  137. { 0x0024, 0x0f030a02 },
  138. { 0x0030, 0x00000001 },
  139. { 0x00b0, 0x00000000 },
  140. { 0x0040, 0x0000000b },
  141. { 0x0044, 0x00000008 },
  142. { 0x0048, 0x00000000 },
  143. { 0x0050, 0x0000000b },
  144. { 0x0054, 0x000c000b },
  145. { 0x0058, 0x00000027 },
  146. { 0x005c, 0x0000001c },
  147. { 0x0060, 0x00000006 },
  148. { 0x0064, 0x00000020 },
  149. { 0x0068, 0x00000008 },
  150. { 0x006c, 0x0000000c },
  151. { 0x0070, 0x00000009 },
  152. { 0x0074, 0x00000012 },
  153. { 0x0078, 0x000000d0 },
  154. { 0x007c, 0x00140005 },
  155. { 0x0080, 0x00050004 },
  156. { 0x0084, 0x70233005 },
  157. { 0x0088, 0x000c0000 },
  158. { 0x008c, 0x00000300 },
  159. { 0x0090, 0x00000040 },
  160. { 0x0100, 0x00000001 },
  161. { 0x00c0, 0x00020001 },
  162. { 0x00c8, 0x20082004 },
  163. { 0x0380, 0x00020002 },
  164. { 0x0390, 0x0000001f },
  165. };
  166. static const struct reg_config dbsc_config5[] = {
  167. { 0x0244, 0x00000011 },
  168. { 0x0290, 0x00000003 },
  169. { 0x02a0, 0x0300c4e1 },
  170. { 0x0290, 0x00000023 },
  171. { 0x02a0, 0x00fcdb60 },
  172. { 0x0290, 0x00000011 },
  173. { 0x02a0, 0x1000040b },
  174. { 0x0290, 0x00000012 },
  175. { 0x02a0, 0x9d9cbb66 },
  176. { 0x0290, 0x00000013 },
  177. { 0x02a0, 0x1a868400 },
  178. { 0x0290, 0x00000014 },
  179. { 0x02a0, 0x300214d8 },
  180. { 0x0290, 0x00000015 },
  181. { 0x02a0, 0x00000d70 },
  182. { 0x0290, 0x00000016 },
  183. { 0x02a0, 0x00000004 },
  184. { 0x0290, 0x00000017 },
  185. { 0x02a0, 0x00000018 },
  186. { 0x0290, 0x0000001a },
  187. { 0x02a0, 0x910035c7 },
  188. { 0x0290, 0x00000004 },
  189. };
  190. static const struct reg_config dbsc_config6[] = {
  191. { 0x0290, 0x00000001 },
  192. { 0x02a0, 0x00000181 },
  193. { 0x0018, 0x11000000 },
  194. { 0x0290, 0x00000004 },
  195. };
  196. static const struct reg_config dbsc_config7[] = {
  197. { 0x0290, 0x00000001 },
  198. { 0x02a0, 0x0000fe01 },
  199. { 0x0304, 0x00000000 },
  200. { 0x00f4, 0x01004c20 },
  201. { 0x00f8, 0x014000aa },
  202. { 0x00e0, 0x00000140 },
  203. { 0x00e4, 0x00081860 },
  204. { 0x00e8, 0x00010000 },
  205. { 0x0290, 0x00000004 },
  206. };
  207. static const struct reg_config dbsc_config8[] = {
  208. { 0x0014, 0x00000001 },
  209. { 0x0010, 0x00000001 },
  210. { 0x0280, 0x00000000 },
  211. };
  212. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  213. unsigned int i;
  214. for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
  215. writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
  216. dbsc_wait(0x2a0);
  217. for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
  218. writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
  219. for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
  220. writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
  221. dbsc_wait(0x240);
  222. for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
  223. writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
  224. dbsc_wait(0x2a0);
  225. for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
  226. writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
  227. dbsc_wait(0x2a0);
  228. for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
  229. writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
  230. dbsc_wait(0x2a0);
  231. for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
  232. writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
  233. }
  234. static void s_init_wait(volatile unsigned int cnt)
  235. {
  236. volatile u32 i = cnt * 0x10000;
  237. while (i-- > 0)
  238. ;
  239. }
  240. #endif
  241. void s_init(void)
  242. {
  243. blanche_init_sys();
  244. qos_init();
  245. blanche_init_pfc();
  246. blanche_init_lbsc();
  247. #if defined(CONFIG_MTD_NOR_FLASH)
  248. s_init_wait(10);
  249. blanche_init_dbsc();
  250. #endif /* CONFIG_MTD_NOR_FLASH */
  251. }
  252. int board_early_init_f(void)
  253. {
  254. /* TMU0 */
  255. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  256. /* QSPI */
  257. mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
  258. return 0;
  259. }
  260. int board_init(void)
  261. {
  262. /* adress of boot parameters */
  263. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  264. return 0;
  265. }
  266. /* Added for BLANCHE(R-CarV2H board) */
  267. int board_eth_init(bd_t *bis)
  268. {
  269. int rc = 0;
  270. #ifdef CONFIG_SMC911X
  271. struct eth_device *dev;
  272. uchar eth_addr[6];
  273. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  274. if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
  275. dev = eth_get_dev_by_index(0);
  276. if (dev) {
  277. eth_env_set_enetaddr("ethaddr", dev->enetaddr);
  278. } else {
  279. printf("blanche: Couldn't get eth device\n");
  280. rc = -1;
  281. }
  282. }
  283. #endif
  284. return rc;
  285. }
  286. int dram_init(void)
  287. {
  288. if (fdtdec_setup_mem_size_base() != 0)
  289. return -EINVAL;
  290. return 0;
  291. }
  292. int dram_init_banksize(void)
  293. {
  294. fdtdec_setup_memory_banksize();
  295. return 0;
  296. }
  297. void reset_cpu(ulong addr)
  298. {
  299. }