pfla02.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/iomux.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/mach-imx/iomux-v3.h>
  14. #include <asm/mach-imx/boot_mode.h>
  15. #include <asm/mach-imx/mxc_i2c.h>
  16. #include <asm/mach-imx/spi.h>
  17. #include <env.h>
  18. #include <linux/errno.h>
  19. #include <asm/gpio.h>
  20. #include <mmc.h>
  21. #include <i2c.h>
  22. #include <fsl_esdhc_imx.h>
  23. #include <nand.h>
  24. #include <miiphy.h>
  25. #include <netdev.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/sections.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  30. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  31. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  32. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  33. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  34. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  35. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  36. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  37. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  38. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  39. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  40. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  41. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  42. #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  43. #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
  44. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  45. #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  46. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  47. #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
  48. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  49. #define GREEN_LED IMX_GPIO_NR(2, 31)
  50. #define RED_LED IMX_GPIO_NR(1, 30)
  51. #define IMX6Q_DRIVE_STRENGTH 0x30
  52. int dram_init(void)
  53. {
  54. gd->ram_size = imx_ddr_size();
  55. return 0;
  56. }
  57. static iomux_v3_cfg_t const uart4_pads[] = {
  58. IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  59. IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  60. };
  61. static iomux_v3_cfg_t const enet_pads[] = {
  62. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  70. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  72. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  79. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80. IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  81. };
  82. static iomux_v3_cfg_t const ecspi3_pads[] = {
  83. IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  84. IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  85. IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  86. IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87. };
  88. static iomux_v3_cfg_t const gpios_pads[] = {
  89. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90. IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91. IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92. IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93. IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94. IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95. IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  97. };
  98. #ifdef CONFIG_CMD_NAND
  99. /* NAND */
  100. static iomux_v3_cfg_t const nfc_pads[] = {
  101. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  102. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  103. IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  104. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  105. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  106. IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  107. IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  108. IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  109. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  110. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  111. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  112. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  113. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  114. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  115. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  116. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  117. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  118. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  119. IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  120. };
  121. #endif
  122. static struct i2c_pads_info i2c_pad_info = {
  123. .scl = {
  124. .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
  125. .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD,
  126. .gp = IMX_GPIO_NR(3, 21)
  127. },
  128. .sda = {
  129. .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
  130. .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD,
  131. .gp = IMX_GPIO_NR(3, 28)
  132. }
  133. };
  134. static struct fsl_esdhc_cfg usdhc_cfg[] = {
  135. {USDHC3_BASE_ADDR,
  136. .max_bus_width = 4},
  137. {.esdhc_base = USDHC2_BASE_ADDR,
  138. .max_bus_width = 4},
  139. };
  140. #if !defined(CONFIG_SPL_BUILD)
  141. static iomux_v3_cfg_t const usdhc2_pads[] = {
  142. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  143. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  144. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  145. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  146. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  147. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  148. IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  149. IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  150. };
  151. #endif
  152. static iomux_v3_cfg_t const usdhc3_pads[] = {
  153. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  154. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  155. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  156. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  157. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  158. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  159. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  160. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  161. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  162. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  163. };
  164. int board_mmc_get_env_dev(int devno)
  165. {
  166. return devno - 1;
  167. }
  168. int board_mmc_getcd(struct mmc *mmc)
  169. {
  170. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  171. int ret = 0;
  172. switch (cfg->esdhc_base) {
  173. case USDHC2_BASE_ADDR:
  174. ret = !gpio_get_value(USDHC2_CD_GPIO);
  175. ret = 1;
  176. break;
  177. case USDHC3_BASE_ADDR:
  178. ret = 1;
  179. break;
  180. }
  181. return ret;
  182. }
  183. #ifndef CONFIG_SPL_BUILD
  184. int board_mmc_init(bd_t *bis)
  185. {
  186. int ret;
  187. int i;
  188. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  189. switch (i) {
  190. case 0:
  191. SETUP_IOMUX_PADS(usdhc3_pads);
  192. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  193. break;
  194. case 1:
  195. SETUP_IOMUX_PADS(usdhc2_pads);
  196. gpio_direction_input(USDHC2_CD_GPIO);
  197. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  198. break;
  199. default:
  200. printf("Warning: you configured more USDHC controllers"
  201. "(%d) then supported by the board (%d)\n",
  202. i + 1, CONFIG_SYS_FSL_USDHC_NUM);
  203. return -EINVAL;
  204. }
  205. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  206. if (ret)
  207. return ret;
  208. }
  209. return 0;
  210. }
  211. #endif
  212. static void setup_iomux_uart(void)
  213. {
  214. SETUP_IOMUX_PADS(uart4_pads);
  215. }
  216. static void setup_iomux_enet(void)
  217. {
  218. SETUP_IOMUX_PADS(enet_pads);
  219. gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
  220. mdelay(10);
  221. gpio_set_value(ENET_PHY_RESET_GPIO, 1);
  222. mdelay(30);
  223. }
  224. static void setup_spi(void)
  225. {
  226. gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
  227. gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
  228. SETUP_IOMUX_PADS(ecspi3_pads);
  229. enable_spi_clk(true, 2);
  230. }
  231. static void setup_gpios(void)
  232. {
  233. SETUP_IOMUX_PADS(gpios_pads);
  234. }
  235. #ifdef CONFIG_CMD_NAND
  236. static void setup_gpmi_nand(void)
  237. {
  238. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  239. /* config gpmi nand iomux */
  240. SETUP_IOMUX_PADS(nfc_pads);
  241. /* gate ENFC_CLK_ROOT clock first,before clk source switch */
  242. clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  243. /* config gpmi and bch clock to 100 MHz */
  244. clrsetbits_le32(&mxc_ccm->cs2cdr,
  245. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  246. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  247. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  248. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  249. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  250. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  251. /* enable ENFC_CLK_ROOT clock */
  252. setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  253. /* enable gpmi and bch clock gating */
  254. setbits_le32(&mxc_ccm->CCGR4,
  255. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  256. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  257. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  258. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  259. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  260. /* enable apbh clock gating */
  261. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  262. }
  263. #endif
  264. /*
  265. * Board revision is coded in 4 GPIOs
  266. */
  267. u32 get_board_rev(void)
  268. {
  269. u32 rev;
  270. int i;
  271. for (i = 0, rev = 0; i < 4; i++)
  272. rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i);
  273. return 16 - rev;
  274. }
  275. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  276. {
  277. if (bus != 2 || (cs != 0))
  278. return -EINVAL;
  279. return IMX_GPIO_NR(4, 24);
  280. }
  281. int board_eth_init(bd_t *bis)
  282. {
  283. setup_iomux_enet();
  284. return cpu_eth_init(bis);
  285. }
  286. int board_early_init_f(void)
  287. {
  288. setup_iomux_uart();
  289. return 0;
  290. }
  291. int board_init(void)
  292. {
  293. /* address of boot parameters */
  294. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  295. #ifdef CONFIG_SYS_I2C_MXC
  296. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);
  297. #endif
  298. #ifdef CONFIG_MXC_SPI
  299. setup_spi();
  300. #endif
  301. setup_gpios();
  302. #ifdef CONFIG_CMD_NAND
  303. setup_gpmi_nand();
  304. #endif
  305. return 0;
  306. }
  307. #ifdef CONFIG_CMD_BMODE
  308. /*
  309. * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
  310. * see Table 8-11 and Table 5-9
  311. * BOOT_CFG1[7] = 1 (boot from NAND)
  312. * BOOT_CFG1[5] = 0 - raw NAND
  313. * BOOT_CFG1[4] = 0 - default pad settings
  314. * BOOT_CFG1[3:2] = 00 - devices = 1
  315. * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
  316. * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
  317. * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
  318. * BOOT_CFG2[0] = 0 - Reset time 12ms
  319. */
  320. static const struct boot_mode board_boot_modes[] = {
  321. /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
  322. {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
  323. {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  324. {NULL, 0},
  325. };
  326. #endif
  327. int board_late_init(void)
  328. {
  329. char buf[10];
  330. #ifdef CONFIG_CMD_BMODE
  331. add_board_boot_modes(board_boot_modes);
  332. #endif
  333. snprintf(buf, sizeof(buf), "%d", get_board_rev());
  334. env_set("board_rev", buf);
  335. return 0;
  336. }
  337. #ifdef CONFIG_SPL_BUILD
  338. #include <asm/arch/mx6-ddr.h>
  339. #include <spl.h>
  340. #include <linux/libfdt.h>
  341. #define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
  342. static void phyflex_err006282_workaround(void)
  343. {
  344. /*
  345. * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
  346. * to the CMIC. If this pin isn't toggled within 10s the boards
  347. * reset. The pin is unconnected on older boards, so we do not
  348. * need a check for older boards before applying this fixup.
  349. */
  350. gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
  351. mdelay(2);
  352. gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
  353. mdelay(2);
  354. gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
  355. gpio_direction_input(MX6_PHYFLEX_ERR006282);
  356. }
  357. static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  358. .dram_sdclk_0 = 0x00000030,
  359. .dram_sdclk_1 = 0x00000030,
  360. .dram_cas = 0x00000030,
  361. .dram_ras = 0x00000030,
  362. .dram_reset = 0x00000030,
  363. .dram_sdcke0 = 0x00003000,
  364. .dram_sdcke1 = 0x00003000,
  365. .dram_sdba2 = 0x00000030,
  366. .dram_sdodt0 = 0x00000030,
  367. .dram_sdodt1 = 0x00000030,
  368. .dram_sdqs0 = 0x00000028,
  369. .dram_sdqs1 = 0x00000028,
  370. .dram_sdqs2 = 0x00000028,
  371. .dram_sdqs3 = 0x00000028,
  372. .dram_sdqs4 = 0x00000028,
  373. .dram_sdqs5 = 0x00000028,
  374. .dram_sdqs6 = 0x00000028,
  375. .dram_sdqs7 = 0x00000028,
  376. .dram_dqm0 = 0x00000028,
  377. .dram_dqm1 = 0x00000028,
  378. .dram_dqm2 = 0x00000028,
  379. .dram_dqm3 = 0x00000028,
  380. .dram_dqm4 = 0x00000028,
  381. .dram_dqm5 = 0x00000028,
  382. .dram_dqm6 = 0x00000028,
  383. .dram_dqm7 = 0x00000028,
  384. };
  385. static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  386. .grp_ddr_type = 0x000C0000,
  387. .grp_ddrmode_ctl = 0x00020000,
  388. .grp_ddrpke = 0x00000000,
  389. .grp_addds = IMX6Q_DRIVE_STRENGTH,
  390. .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
  391. .grp_ddrmode = 0x00020000,
  392. .grp_b0ds = 0x00000028,
  393. .grp_b1ds = 0x00000028,
  394. .grp_b2ds = 0x00000028,
  395. .grp_b3ds = 0x00000028,
  396. .grp_b4ds = 0x00000028,
  397. .grp_b5ds = 0x00000028,
  398. .grp_b6ds = 0x00000028,
  399. .grp_b7ds = 0x00000028,
  400. };
  401. static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
  402. .p0_mpwldectrl0 = 0x00110011,
  403. .p0_mpwldectrl1 = 0x00240024,
  404. .p1_mpwldectrl0 = 0x00260038,
  405. .p1_mpwldectrl1 = 0x002C0038,
  406. .p0_mpdgctrl0 = 0x03400350,
  407. .p0_mpdgctrl1 = 0x03440340,
  408. .p1_mpdgctrl0 = 0x034C0354,
  409. .p1_mpdgctrl1 = 0x035C033C,
  410. .p0_mprddlctl = 0x322A2A2A,
  411. .p1_mprddlctl = 0x302C2834,
  412. .p0_mpwrdlctl = 0x34303834,
  413. .p1_mpwrdlctl = 0x422A3E36,
  414. };
  415. /* Index in RAM Chip array */
  416. enum {
  417. RAM_MT64K,
  418. RAM_MT128K,
  419. RAM_MT256K
  420. };
  421. static struct mx6_ddr3_cfg mt41k_xx[] = {
  422. /* MT41K64M16JT-125 (1Gb density) */
  423. {
  424. .mem_speed = 1600,
  425. .density = 1,
  426. .width = 16,
  427. .banks = 8,
  428. .rowaddr = 13,
  429. .coladdr = 10,
  430. .pagesz = 2,
  431. .trcd = 1375,
  432. .trcmin = 4875,
  433. .trasmin = 3500,
  434. .SRT = 1,
  435. },
  436. /* MT41K256M16JT-125 (2Gb density) */
  437. {
  438. .mem_speed = 1600,
  439. .density = 2,
  440. .width = 16,
  441. .banks = 8,
  442. .rowaddr = 14,
  443. .coladdr = 10,
  444. .pagesz = 2,
  445. .trcd = 1375,
  446. .trcmin = 4875,
  447. .trasmin = 3500,
  448. .SRT = 1,
  449. },
  450. /* MT41K256M16JT-125 (4Gb density) */
  451. {
  452. .mem_speed = 1600,
  453. .density = 4,
  454. .width = 16,
  455. .banks = 8,
  456. .rowaddr = 15,
  457. .coladdr = 10,
  458. .pagesz = 2,
  459. .trcd = 1375,
  460. .trcmin = 4875,
  461. .trasmin = 3500,
  462. .SRT = 1,
  463. }
  464. };
  465. static void ccgr_init(void)
  466. {
  467. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  468. writel(0x00C03F3F, &ccm->CCGR0);
  469. writel(0x0030FC03, &ccm->CCGR1);
  470. writel(0x0FFFC000, &ccm->CCGR2);
  471. writel(0x3FF00000, &ccm->CCGR3);
  472. writel(0x00FFF300, &ccm->CCGR4);
  473. writel(0x0F0000C3, &ccm->CCGR5);
  474. writel(0x000003FF, &ccm->CCGR6);
  475. }
  476. static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
  477. struct mx6_ddr3_cfg *mem_ddr)
  478. {
  479. mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  480. mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
  481. }
  482. int board_mmc_init(bd_t *bis)
  483. {
  484. if (spl_boot_device() == BOOT_DEVICE_SPI)
  485. printf("MMC SEtup, Boot SPI");
  486. SETUP_IOMUX_PADS(usdhc3_pads);
  487. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  488. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  489. usdhc_cfg[0].max_bus_width = 4;
  490. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  491. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  492. }
  493. void board_boot_order(u32 *spl_boot_list)
  494. {
  495. spl_boot_list[0] = spl_boot_device();
  496. printf("Boot device %x\n", spl_boot_list[0]);
  497. switch (spl_boot_list[0]) {
  498. case BOOT_DEVICE_SPI:
  499. spl_boot_list[1] = BOOT_DEVICE_UART;
  500. break;
  501. case BOOT_DEVICE_MMC1:
  502. spl_boot_list[1] = BOOT_DEVICE_SPI;
  503. spl_boot_list[2] = BOOT_DEVICE_UART;
  504. break;
  505. default:
  506. printf("Boot device %x\n", spl_boot_list[0]);
  507. }
  508. }
  509. /*
  510. * This is used because get_ram_size() does not
  511. * take care of cache, resulting a wrong size
  512. * pfla02 has just 1, 2 or 4 GB option
  513. * Function checks for mirrors in the first CS
  514. */
  515. #define RAM_TEST_PATTERN 0xaa5555aa
  516. #define MIN_BANK_SIZE (512 * 1024 * 1024)
  517. static unsigned int pfla02_detect_chiptype(void)
  518. {
  519. u32 *p, *p1;
  520. unsigned int offset = MIN_BANK_SIZE;
  521. int i;
  522. for (i = 0; i < 2; i++) {
  523. p = (u32 *)PHYS_SDRAM;
  524. p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset);
  525. *p1 = 0;
  526. *p = RAM_TEST_PATTERN;
  527. /*
  528. * This is required to detect mirroring
  529. * else we read back values from cache
  530. */
  531. flush_dcache_all();
  532. if (*p == *p1)
  533. return i;
  534. }
  535. return RAM_MT256K;
  536. }
  537. void board_init_f(ulong dummy)
  538. {
  539. unsigned int ramchip;
  540. struct mx6_ddr_sysinfo sysinfo = {
  541. /* width of data bus:0=16,1=32,2=64 */
  542. .dsize = 2,
  543. /* config for full 4GB range so that get_mem_size() works */
  544. .cs_density = 32, /* 512 MB */
  545. /* single chip select */
  546. #if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
  547. .ncs = 1,
  548. #else
  549. .ncs = 2,
  550. #endif
  551. .cs1_mirror = 1,
  552. .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  553. .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
  554. .walat = 1, /* Write additional latency */
  555. .ralat = 5, /* Read additional latency */
  556. .mif3_mode = 3, /* Command prediction working mode */
  557. .bi_on = 1, /* Bank interleaving enabled */
  558. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  559. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  560. .ddr_type = DDR_TYPE_DDR3,
  561. .refsel = 1, /* Refresh cycles at 32KHz */
  562. .refr = 7, /* 8 refresh commands per refresh cycle */
  563. };
  564. #ifdef CONFIG_CMD_NAND
  565. /* Enable NAND */
  566. setup_gpmi_nand();
  567. #endif
  568. /* setup clock gating */
  569. ccgr_init();
  570. /* setup AIPS and disable watchdog */
  571. arch_cpu_init();
  572. /* setup AXI */
  573. gpr_init();
  574. board_early_init_f();
  575. /* setup GP timer */
  576. timer_init();
  577. /* UART clocks enabled and gd valid - init serial console */
  578. preloader_console_init();
  579. setup_spi();
  580. setup_gpios();
  581. /* DDR initialization */
  582. spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
  583. ramchip = pfla02_detect_chiptype();
  584. debug("Detected chip %d\n", ramchip);
  585. #if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
  586. switch (ramchip) {
  587. case RAM_MT64K:
  588. sysinfo.cs_density = 6;
  589. break;
  590. case RAM_MT128K:
  591. sysinfo.cs_density = 10;
  592. break;
  593. case RAM_MT256K:
  594. sysinfo.cs_density = 18;
  595. break;
  596. }
  597. #endif
  598. spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
  599. /* Clear the BSS. */
  600. memset(__bss_start, 0, __bss_end - __bss_start);
  601. phyflex_err006282_workaround();
  602. /* load/boot image from boot device */
  603. board_init_r(NULL, 0);
  604. }
  605. #endif