pcm052.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
  5. *
  6. * Copyright 2013 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux-vf610.h>
  12. #include <asm/arch/ddrmc-vf610.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <env.h>
  16. #include <led.h>
  17. #include <environment.h>
  18. #include <miiphy.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static struct ddrmc_cr_setting pcm052_cr_settings[] = {
  21. /* not in the datasheets, but in the original code */
  22. { 0x00002000, 105 },
  23. { 0x00000020, 110 },
  24. /* AXI */
  25. { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
  26. { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
  27. { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
  28. DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
  29. { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
  30. DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
  31. { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
  32. DDRMC_CR122_AXI0_PRIRLX(100), 122 },
  33. { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
  34. DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
  35. { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
  36. { DDRMC_CR126_PHY_RDLAT(11), 126 },
  37. { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
  38. { DDRMC_CR137_PHYCTL_DL(2), 137 },
  39. { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
  40. DDRMC_CR139_PHY_WRLV_DLL(3) |
  41. DDRMC_CR139_PHY_WRLV_EN(3), 139 },
  42. { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
  43. DDRMC_CR154_PAD_ZQ_MODE(1) |
  44. DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
  45. DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
  46. { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
  47. { DDRMC_CR158_TWR(6), 158 },
  48. { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
  49. DDRMC_CR161_TODTH_WR(6), 161 },
  50. /* end marker */
  51. { 0, -1 }
  52. };
  53. /* PHY settings -- most of them differ from default in imx-regs.h */
  54. #define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213
  55. #define PCM052_DDRMC_PHY_CTRL 0x00290000
  56. #define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00
  57. #define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020
  58. static struct ddrmc_phy_setting pcm052_phy_settings[] = {
  59. { PCM052_DDRMC_PHY_DQ_TIMING, 0 },
  60. { PCM052_DDRMC_PHY_DQ_TIMING, 16 },
  61. { PCM052_DDRMC_PHY_DQ_TIMING, 32 },
  62. { PCM052_DDRMC_PHY_DQ_TIMING, 48 },
  63. { DDRMC_PHY_DQS_TIMING, 1 },
  64. { DDRMC_PHY_DQS_TIMING, 17 },
  65. { DDRMC_PHY_DQS_TIMING, 33 },
  66. { DDRMC_PHY_DQS_TIMING, 49 },
  67. { PCM052_DDRMC_PHY_CTRL, 2 },
  68. { PCM052_DDRMC_PHY_CTRL, 18 },
  69. { PCM052_DDRMC_PHY_CTRL, 34 },
  70. { DDRMC_PHY_MASTER_CTRL, 3 },
  71. { DDRMC_PHY_MASTER_CTRL, 19 },
  72. { DDRMC_PHY_MASTER_CTRL, 35 },
  73. { PCM052_DDRMC_PHY_SLAVE_CTRL, 4 },
  74. { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
  75. { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
  76. { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
  77. { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
  78. /* end marker */
  79. { 0, -1 }
  80. };
  81. int dram_init(void)
  82. {
  83. #if defined(CONFIG_TARGET_PCM052)
  84. static const struct ddr3_jedec_timings pcm052_ddr_timings = {
  85. .tinit = 5,
  86. .trst_pwron = 80000,
  87. .cke_inactive = 200000,
  88. .wrlat = 5,
  89. .caslat_lin = 12,
  90. .trc = 6,
  91. .trrd = 4,
  92. .tccd = 4,
  93. .tbst_int_interval = 4,
  94. .tfaw = 18,
  95. .trp = 6,
  96. .twtr = 4,
  97. .tras_min = 15,
  98. .tmrd = 4,
  99. .trtp = 4,
  100. .tras_max = 14040,
  101. .tmod = 12,
  102. .tckesr = 4,
  103. .tcke = 3,
  104. .trcd_int = 6,
  105. .tras_lockout = 1,
  106. .tdal = 10,
  107. .bstlen = 3,
  108. .tdll = 512,
  109. .trp_ab = 6,
  110. .tref = 1542,
  111. .trfc = 64,
  112. .tref_int = 5,
  113. .tpdex = 3,
  114. .txpdll = 10,
  115. .txsnr = 68,
  116. .txsr = 506,
  117. .cksrx = 5,
  118. .cksre = 5,
  119. .freq_chg_en = 1,
  120. .zqcl = 256,
  121. .zqinit = 512,
  122. .zqcs = 64,
  123. .ref_per_zq = 64,
  124. .zqcs_rotate = 1,
  125. .aprebit = 10,
  126. .cmd_age_cnt = 255,
  127. .age_cnt = 255,
  128. .q_fullness = 0,
  129. .odt_rd_mapcs0 = 1,
  130. .odt_wr_mapcs0 = 1,
  131. .wlmrd = 40,
  132. .wldqsen = 25,
  133. };
  134. const int row_diff = 2;
  135. #elif defined(CONFIG_TARGET_BK4R1)
  136. static const struct ddr3_jedec_timings pcm052_ddr_timings = {
  137. .tinit = 5,
  138. .trst_pwron = 80000,
  139. .cke_inactive = 200000,
  140. .wrlat = 5,
  141. .caslat_lin = 12,
  142. .trc = 6,
  143. .trrd = 4,
  144. .tccd = 4,
  145. .tbst_int_interval = 0,
  146. .tfaw = 16,
  147. .trp = 6,
  148. .twtr = 4,
  149. .tras_min = 15,
  150. .tmrd = 4,
  151. .trtp = 4,
  152. .tras_max = 28080,
  153. .tmod = 12,
  154. .tckesr = 4,
  155. .tcke = 3,
  156. .trcd_int = 6,
  157. .tras_lockout = 1,
  158. .tdal = 12,
  159. .bstlen = 3,
  160. .tdll = 512,
  161. .trp_ab = 6,
  162. .tref = 3120,
  163. .trfc = 104,
  164. .tref_int = 0,
  165. .tpdex = 3,
  166. .txpdll = 10,
  167. .txsnr = 108,
  168. .txsr = 512,
  169. .cksrx = 5,
  170. .cksre = 5,
  171. .freq_chg_en = 1,
  172. .zqcl = 256,
  173. .zqinit = 512,
  174. .zqcs = 64,
  175. .ref_per_zq = 64,
  176. .zqcs_rotate = 1,
  177. .aprebit = 10,
  178. .cmd_age_cnt = 255,
  179. .age_cnt = 255,
  180. .q_fullness = 0,
  181. .odt_rd_mapcs0 = 1,
  182. .odt_wr_mapcs0 = 1,
  183. .wlmrd = 40,
  184. .wldqsen = 25,
  185. };
  186. const int row_diff = 1;
  187. #else /* Unknown PCM052 variant */
  188. #error DDR characteristics undefined for this target. Please define them.
  189. #endif
  190. ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
  191. pcm052_phy_settings, 1, row_diff);
  192. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  193. return 0;
  194. }
  195. static void clock_init(void)
  196. {
  197. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  198. struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
  199. clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
  200. CCM_CCGR0_UART1_CTRL_MASK);
  201. clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
  202. CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
  203. clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
  204. CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
  205. CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
  206. CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
  207. CCM_CCGR2_QSPI0_CTRL_MASK);
  208. clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
  209. CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
  210. clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
  211. CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
  212. CCM_CCGR4_GPC_CTRL_MASK);
  213. clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
  214. CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
  215. clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
  216. CCM_CCGR7_SDHC1_CTRL_MASK);
  217. clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
  218. CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
  219. clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
  220. CCM_CCGR10_NFC_CTRL_MASK);
  221. clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
  222. ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
  223. clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
  224. ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
  225. clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
  226. CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
  227. clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
  228. CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
  229. CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
  230. CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
  231. CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
  232. CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
  233. CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
  234. clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
  235. CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
  236. CCM_CACRR_ARM_CLK_DIV(0));
  237. clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
  238. CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
  239. CCM_CSCMR1_QSPI0_CLK_SEL(3) |
  240. CCM_CSCMR1_NFC_CLK_SEL(0));
  241. clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
  242. CCM_CSCDR1_RMII_CLK_EN);
  243. clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
  244. CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
  245. CCM_CSCDR2_NFC_EN);
  246. clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
  247. CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
  248. CCM_CSCDR3_QSPI0_X2_DIV(1) |
  249. CCM_CSCDR3_QSPI0_X4_DIV(3) |
  250. CCM_CSCDR3_NFC_PRE_DIV(5));
  251. clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
  252. CCM_CSCMR2_RMII_CLK_SEL(0));
  253. }
  254. static void mscm_init(void)
  255. {
  256. struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
  257. int i;
  258. for (i = 0; i < MSCM_IRSPRC_NUM; i++)
  259. writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
  260. }
  261. int board_early_init_f(void)
  262. {
  263. clock_init();
  264. mscm_init();
  265. return 0;
  266. }
  267. int board_init(void)
  268. {
  269. struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
  270. /* address of boot parameters */
  271. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  272. /*
  273. * Enable external 32K Oscillator
  274. *
  275. * The internal clock experiences significant drift
  276. * so we must use the external oscillator in order
  277. * to maintain correct time in the hwclock
  278. */
  279. setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
  280. return 0;
  281. }
  282. #ifdef CONFIG_TARGET_BK4R1
  283. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  284. {
  285. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  286. struct fuse_bank *bank = &ocotp->bank[4];
  287. struct fuse_bank4_regs *fuse =
  288. (struct fuse_bank4_regs *)bank->fuse_regs;
  289. u32 value;
  290. /*
  291. * BK4 has different layout of stored MAC address
  292. * than one used in imx_get_mac_from_fuse() @ generic.c
  293. */
  294. switch (dev_id) {
  295. case 0:
  296. value = readl(&fuse->mac_addr1);
  297. mac[0] = value >> 8;
  298. mac[1] = value;
  299. value = readl(&fuse->mac_addr0);
  300. mac[2] = value >> 24;
  301. mac[3] = value >> 16;
  302. mac[4] = value >> 8;
  303. mac[5] = value;
  304. break;
  305. case 1:
  306. value = readl(&fuse->mac_addr2);
  307. mac[0] = value >> 24;
  308. mac[1] = value >> 16;
  309. mac[2] = value >> 8;
  310. mac[3] = value;
  311. value = readl(&fuse->mac_addr1);
  312. mac[4] = value >> 24;
  313. mac[5] = value >> 16;
  314. break;
  315. }
  316. }
  317. int board_late_init(void)
  318. {
  319. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  320. u32 reg;
  321. if (IS_ENABLED(CONFIG_LED))
  322. led_default_state();
  323. /*
  324. * BK4r1 handle emergency/service SD card boot
  325. * Checking the SBMR1 register BOOTCFG1 byte:
  326. * NAND:
  327. * bit [2] - NAND data width - 16
  328. * bit [5] - NAND fast boot
  329. * bit [7] = 1 - NAND as a source of booting
  330. * SD card (0x64):
  331. * bit [4] = 0 - SD card source
  332. * bit [6] = 1 - SD/MMC source
  333. */
  334. reg = readl(&psrc->sbmr1);
  335. if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
  336. !(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
  337. printf("------ SD card boot -------\n");
  338. set_default_env("!LVFBootloader", 0);
  339. env_set("bootcmd",
  340. "run prepare_install_bk4r1_envs; run install_bk4r1rs");
  341. }
  342. return 0;
  343. }
  344. /**
  345. * KSZ8081
  346. */
  347. #define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f
  348. #define RMII_50MHz_CLOCK 0x8180
  349. int board_phy_config(struct phy_device *phydev)
  350. {
  351. /* Set 50 MHz reference clock */
  352. phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
  353. RMII_50MHz_CLOCK);
  354. return genphy_config(phydev);
  355. }
  356. #endif /* CONFIG_TARGET_BK4R1 */
  357. int checkboard(void)
  358. {
  359. #ifdef CONFIG_TARGET_BK4R1
  360. puts("Board: BK4r1 (L333)\n");
  361. #else
  362. puts("Board: PCM-052\n");
  363. #endif
  364. return 0;
  365. }