imx6logic.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Logic PD, Inc.
  4. *
  5. * Author: Adam Ford <aford173@gmail.com>
  6. *
  7. * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
  8. * and updates by Jagan Teki <jagan@amarulasolutions.com>
  9. */
  10. #include <common.h>
  11. #include <env.h>
  12. #include <miiphy.h>
  13. #include <input.h>
  14. #include <mmc.h>
  15. #include <fsl_esdhc_imx.h>
  16. #include <asm/io.h>
  17. #include <asm/gpio.h>
  18. #include <linux/sizes.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/crm_regs.h>
  21. #include <asm/arch/iomux.h>
  22. #include <asm/arch/mxc_hdmi.h>
  23. #include <asm/arch/mx6-pins.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/mach-imx/boot_mode.h>
  26. #include <asm/mach-imx/iomux-v3.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  29. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  30. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  31. #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  32. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  33. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  34. int dram_init(void)
  35. {
  36. gd->ram_size = imx_ddr_size();
  37. return 0;
  38. }
  39. static iomux_v3_cfg_t const uart1_pads[] = {
  40. MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  41. MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  42. };
  43. static iomux_v3_cfg_t const uart2_pads[] = {
  44. MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  45. MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  46. MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  47. MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  48. };
  49. static iomux_v3_cfg_t const uart3_pads[] = {
  50. MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  51. MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  52. MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  53. MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  54. };
  55. static void setup_iomux_uart(void)
  56. {
  57. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  58. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  59. imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  60. }
  61. static iomux_v3_cfg_t const nand_pads[] = {
  62. MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  63. MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  64. MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  65. MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  66. MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  67. MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  68. MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  69. MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  70. MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  71. MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  72. MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  73. MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  74. MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  75. MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  76. MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  77. };
  78. static void setup_nand_pins(void)
  79. {
  80. imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  81. }
  82. static int ar8031_phy_fixup(struct phy_device *phydev)
  83. {
  84. unsigned short val;
  85. /* To enable AR8031 output a 125MHz clk from CLK_25M */
  86. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  87. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  88. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  89. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  90. val &= 0xffe3;
  91. val |= 0x18;
  92. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  93. /* introduce tx clock delay */
  94. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  95. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  96. val |= 0x0100;
  97. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  98. return 0;
  99. }
  100. int board_phy_config(struct phy_device *phydev)
  101. {
  102. ar8031_phy_fixup(phydev);
  103. if (phydev->drv->config)
  104. phydev->drv->config(phydev);
  105. return 0;
  106. }
  107. /*
  108. * Do not overwrite the console
  109. * Use always serial for U-Boot console
  110. */
  111. int overwrite_console(void)
  112. {
  113. return 1;
  114. }
  115. int board_early_init_f(void)
  116. {
  117. setup_iomux_uart();
  118. setup_nand_pins();
  119. return 0;
  120. }
  121. int board_init(void)
  122. {
  123. /* address of boot parameters */
  124. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  125. return 0;
  126. }
  127. int board_late_init(void)
  128. {
  129. env_set("board_name", "imx6logic");
  130. if (is_mx6dq()) {
  131. env_set("board_rev", "MX6DQ");
  132. if (!env_get("fdt_file"))
  133. env_set("fdt_file", "imx6q-logicpd.dtb");
  134. }
  135. return 0;
  136. }
  137. #ifdef CONFIG_SPL_BUILD
  138. #include <asm/arch/mx6-ddr.h>
  139. #include <asm/arch/mx6q-ddr.h>
  140. #include <spl.h>
  141. #include <linux/libfdt.h>
  142. #ifdef CONFIG_SPL_OS_BOOT
  143. int spl_start_uboot(void)
  144. {
  145. /* break into full u-boot on 'c' */
  146. if (serial_tstc() && serial_getc() == 'c')
  147. return 1;
  148. return 0;
  149. }
  150. #endif
  151. /* SD interface */
  152. #define USDHC_PAD_CTRL \
  153. (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  154. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  155. static iomux_v3_cfg_t const usdhc1_pads[] = {
  156. MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  157. MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  158. MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  159. MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  160. MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  161. MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  162. };
  163. static iomux_v3_cfg_t const usdhc2_pads[] = {
  164. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  165. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  166. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  167. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  168. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  169. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  170. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  171. };
  172. #ifdef CONFIG_FSL_ESDHC_IMX
  173. struct fsl_esdhc_cfg usdhc_cfg[] = {
  174. {USDHC1_BASE_ADDR}, /* SOM */
  175. {USDHC2_BASE_ADDR} /* Baseboard */
  176. };
  177. int board_mmc_init(bd_t *bis)
  178. {
  179. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  180. unsigned int reg = readl(&psrc->sbmr1) >> 11;
  181. /*
  182. * Upon reading BOOT_CFG register the following map is done:
  183. * Bit 11 and 12 of BOOT_CFG register can determine the current
  184. * mmc port
  185. * 0x1 SD1-SOM
  186. * 0x2 SD2-Baseboard
  187. */
  188. reg &= 0x3; /* Only care about bottom 2 bits */
  189. switch (reg) {
  190. case 0:
  191. SETUP_IOMUX_PADS(usdhc1_pads);
  192. break;
  193. case 1:
  194. SETUP_IOMUX_PADS(usdhc2_pads);
  195. break;
  196. }
  197. return 0;
  198. }
  199. #endif
  200. static void ccgr_init(void)
  201. {
  202. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  203. writel(0x00C03F3F, &ccm->CCGR0);
  204. writel(0x0030FC03, &ccm->CCGR1);
  205. writel(0x0FFFC000, &ccm->CCGR2);
  206. writel(0x3FF00000, &ccm->CCGR3);
  207. writel(0xFFFFF300, &ccm->CCGR4);
  208. writel(0x0F0000F3, &ccm->CCGR5);
  209. writel(0x00000FFF, &ccm->CCGR6);
  210. }
  211. static int mx6q_dcd_table[] = {
  212. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  213. MX6_IOM_GRP_DDRPKE, 0x00000000,
  214. MX6_IOM_DRAM_SDCLK_0, 0x00000030,
  215. MX6_IOM_DRAM_SDCLK_1, 0x00000030,
  216. MX6_IOM_DRAM_CAS, 0x00000030,
  217. MX6_IOM_DRAM_RAS, 0x00000030,
  218. MX6_IOM_GRP_ADDDS, 0x00000030,
  219. MX6_IOM_DRAM_RESET, 0x00000030,
  220. MX6_IOM_DRAM_SDBA2, 0x00000000,
  221. MX6_IOM_DRAM_SDODT0, 0x00000030,
  222. MX6_IOM_DRAM_SDODT1, 0x00000030,
  223. MX6_IOM_GRP_CTLDS, 0x00000030,
  224. MX6_IOM_DDRMODE_CTL, 0x00020000,
  225. MX6_IOM_DRAM_SDQS0, 0x00000030,
  226. MX6_IOM_DRAM_SDQS1, 0x00000030,
  227. MX6_IOM_DRAM_SDQS2, 0x00000030,
  228. MX6_IOM_DRAM_SDQS3, 0x00000030,
  229. MX6_IOM_GRP_DDRMODE, 0x00020000,
  230. MX6_IOM_GRP_B0DS, 0x00000030,
  231. MX6_IOM_GRP_B1DS, 0x00000030,
  232. MX6_IOM_GRP_B2DS, 0x00000030,
  233. MX6_IOM_GRP_B3DS, 0x00000030,
  234. MX6_IOM_DRAM_DQM0, 0x00000030,
  235. MX6_IOM_DRAM_DQM1, 0x00000030,
  236. MX6_IOM_DRAM_DQM2, 0x00000030,
  237. MX6_IOM_DRAM_DQM3, 0x00000030,
  238. MX6_MMDC_P0_MDSCR, 0x00008000,
  239. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  240. MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
  241. MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
  242. MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
  243. MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
  244. MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
  245. MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
  246. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  247. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  248. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  249. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  250. MX6_MMDC_P0_MPMUR0, 0x00000800,
  251. MX6_MMDC_P0_MDPDC, 0x00020036,
  252. MX6_MMDC_P0_MDOTC, 0x09444040,
  253. MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
  254. MX6_MMDC_P0_MDCFG1, 0xFF328F64,
  255. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  256. MX6_MMDC_P0_MDMISC, 0x00011740,
  257. MX6_MMDC_P0_MDSCR, 0x00008000,
  258. MX6_MMDC_P0_MDRWD, 0x000026D2,
  259. MX6_MMDC_P0_MDOR, 0x00BE1023,
  260. MX6_MMDC_P0_MDASP, 0x00000047,
  261. MX6_MMDC_P0_MDCTL, 0x85190000,
  262. MX6_MMDC_P0_MDSCR, 0x00888032,
  263. MX6_MMDC_P0_MDSCR, 0x00008033,
  264. MX6_MMDC_P0_MDSCR, 0x00008031,
  265. MX6_MMDC_P0_MDSCR, 0x19408030,
  266. MX6_MMDC_P0_MDSCR, 0x04008040,
  267. MX6_MMDC_P0_MDREF, 0x00007800,
  268. MX6_MMDC_P0_MPODTCTRL, 0x00000007,
  269. MX6_MMDC_P0_MDPDC, 0x00025576,
  270. MX6_MMDC_P0_MAPSR, 0x00011006,
  271. MX6_MMDC_P0_MDSCR, 0x00000000,
  272. /* enable AXI cache for VDOA/VPU/IPU */
  273. MX6_IOMUXC_GPR4, 0xF00000CF,
  274. /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  275. MX6_IOMUXC_GPR6, 0x007F007F,
  276. MX6_IOMUXC_GPR7, 0x007F007F,
  277. };
  278. static void ddr_init(int *table, int size)
  279. {
  280. int i;
  281. for (i = 0; i < size / 2 ; i++)
  282. writel(table[2 * i + 1], table[2 * i]);
  283. }
  284. static void spl_dram_init(void)
  285. {
  286. if (is_mx6dq())
  287. ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
  288. }
  289. void board_init_f(ulong dummy)
  290. {
  291. /* DDR initialization */
  292. spl_dram_init();
  293. /* setup AIPS and disable watchdog */
  294. arch_cpu_init();
  295. ccgr_init();
  296. gpr_init();
  297. /* iomux and setup of uart and NAND pins */
  298. board_early_init_f();
  299. /* setup GP timer */
  300. timer_init();
  301. /* UART clocks enabled and gd valid - init serial console */
  302. preloader_console_init();
  303. /* Clear the BSS. */
  304. memset(__bss_start, 0, __bss_end - __bss_start);
  305. /* load/boot image from boot device */
  306. board_init_r(NULL, 0);
  307. }
  308. #endif