display5.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/mx6-ddr.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <env.h>
  16. #include <errno.h>
  17. #include <asm/gpio.h>
  18. #include <malloc.h>
  19. #include <asm/mach-imx/iomux-v3.h>
  20. #include <asm/mach-imx/mxc_i2c.h>
  21. #include <asm/mach-imx/boot_mode.h>
  22. #include <asm/mach-imx/spi.h>
  23. #include <mmc.h>
  24. #include <fsl_esdhc_imx.h>
  25. #include <miiphy.h>
  26. #include <netdev.h>
  27. #include <i2c.h>
  28. #include <environment.h>
  29. #include <dm.h>
  30. #include <dm/platform_data/serial_mxc.h>
  31. #include <dm/platdata.h>
  32. #ifndef CONFIG_MXC_SPI
  33. #error "CONFIG_SPI must be set for this board"
  34. #error "Please check your config file"
  35. #endif
  36. #include "common.h"
  37. DECLARE_GLOBAL_DATA_PTR;
  38. static bool hw_ids_valid;
  39. static bool sw_ids_valid;
  40. static u32 cpu_id;
  41. static u32 unit_id;
  42. #define EM_PAD IMX_GPIO_NR(3, 29)
  43. #define SW0 IMX_GPIO_NR(2, 4)
  44. #define SW1 IMX_GPIO_NR(2, 5)
  45. #define SW2 IMX_GPIO_NR(2, 6)
  46. #define SW3 IMX_GPIO_NR(2, 7)
  47. #define HW0 IMX_GPIO_NR(6, 7)
  48. #define HW1 IMX_GPIO_NR(6, 9)
  49. #define HW2 IMX_GPIO_NR(6, 10)
  50. #define HW3 IMX_GPIO_NR(6, 11)
  51. #define HW4 IMX_GPIO_NR(4, 7)
  52. #define HW5 IMX_GPIO_NR(4, 11)
  53. #define HW6 IMX_GPIO_NR(4, 13)
  54. #define HW7 IMX_GPIO_NR(4, 15)
  55. int gpio_table_sw_ids[] = {
  56. SW0, SW1, SW2, SW3
  57. };
  58. const char *gpio_table_sw_ids_names[] = {
  59. "sw0", "sw1", "sw2", "sw3"
  60. };
  61. int gpio_table_hw_ids[] = {
  62. HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7
  63. };
  64. const char *gpio_table_hw_ids_names[] = {
  65. "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
  66. };
  67. static int get_board_id(int *ids, const char **c, int size,
  68. bool *valid, u32 *id)
  69. {
  70. int i, ret, val;
  71. *valid = false;
  72. for (i = 0; i < size; i++) {
  73. ret = gpio_request(ids[i], c[i]);
  74. if (ret) {
  75. printf("Can't request SWx gpios\n");
  76. return ret;
  77. }
  78. }
  79. for (i = 0; i < size; i++) {
  80. ret = gpio_direction_input(ids[i]);
  81. if (ret) {
  82. printf("Can't set SWx gpios direction\n");
  83. return ret;
  84. }
  85. }
  86. for (i = 0; i < size; i++) {
  87. val = gpio_get_value(ids[i]);
  88. if (val < 0) {
  89. printf("Can't get SW%d ID\n", i);
  90. *id = 0;
  91. return val;
  92. }
  93. *id |= val << i;
  94. }
  95. *valid = true;
  96. return 0;
  97. }
  98. int dram_init(void)
  99. {
  100. gd->ram_size = imx_ddr_size();
  101. return 0;
  102. }
  103. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  104. /* I2C1: TFA9879 */
  105. struct i2c_pads_info i2c_pad_info0 = {
  106. .scl = {
  107. .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  108. .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  109. .gp = IMX_GPIO_NR(3, 21)
  110. },
  111. .sda = {
  112. .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  113. .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  114. .gp = IMX_GPIO_NR(3, 28)
  115. }
  116. };
  117. /* I2C2: TIVO TM4C123 */
  118. struct i2c_pads_info i2c_pad_info1 = {
  119. .scl = {
  120. .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  121. .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  122. .gp = IMX_GPIO_NR(2, 30)
  123. },
  124. .sda = {
  125. .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
  126. .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
  127. .gp = IMX_GPIO_NR(3, 16)
  128. }
  129. };
  130. /* I2C3: PMIC PF0100, EEPROM AT24C256C */
  131. struct i2c_pads_info i2c_pad_info2 = {
  132. .scl = {
  133. .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
  134. .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
  135. .gp = IMX_GPIO_NR(3, 17)
  136. },
  137. .sda = {
  138. .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
  139. .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
  140. .gp = IMX_GPIO_NR(3, 18)
  141. }
  142. };
  143. iomux_v3_cfg_t const misc_pads[] = {
  144. /* Prod ID GPIO pins */
  145. MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  146. MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  147. MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  148. MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  149. /* HW revision GPIO pins */
  150. MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  151. MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  152. MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  153. MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  154. MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  155. MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  156. MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
  157. MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  158. /* XTALOSC */
  159. MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
  160. /* Emergency recovery pin */
  161. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  162. };
  163. #ifdef CONFIG_FSL_ESDHC_IMX
  164. struct fsl_esdhc_cfg usdhc_cfg[1] = {
  165. { USDHC4_BASE_ADDR, 0, 8, },
  166. };
  167. int board_mmc_getcd(struct mmc *mmc)
  168. {
  169. return 1;
  170. }
  171. int board_mmc_init(bd_t *bis)
  172. {
  173. displ5_set_iomux_usdhc();
  174. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  175. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  176. }
  177. #endif /* CONFIG_FSL_ESDHC_IMX */
  178. static void displ5_setup_ecspi(void)
  179. {
  180. int ret;
  181. displ5_set_iomux_ecspi();
  182. ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0");
  183. if (!ret)
  184. gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
  185. ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp");
  186. if (!ret)
  187. gpio_direction_output(IMX_GPIO_NR(7, 0), 1);
  188. }
  189. #ifdef CONFIG_FEC_MXC
  190. iomux_v3_cfg_t const enet_pads[] = {
  191. MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  192. MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
  193. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  194. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  195. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  196. /* for old evalboard with R159 present and R160 not populated */
  197. MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  198. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  199. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  200. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  201. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  202. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  203. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  204. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  205. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  206. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  207. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  208. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  209. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  210. /*INT#_GBE*/
  211. MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  212. };
  213. static void setup_iomux_enet(void)
  214. {
  215. SETUP_IOMUX_PADS(enet_pads);
  216. gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/
  217. }
  218. static int setup_mac_from_fuse(void)
  219. {
  220. unsigned char enetaddr[6];
  221. int ret;
  222. ret = eth_env_get_enetaddr("ethaddr", enetaddr);
  223. if (ret) /* ethaddr is already set */
  224. return 0;
  225. imx_get_mac_from_fuse(0, enetaddr);
  226. if (is_valid_ethaddr(enetaddr)) {
  227. eth_env_set_enetaddr("ethaddr", enetaddr);
  228. return 0;
  229. }
  230. return 0;
  231. }
  232. int board_eth_init(bd_t *bd)
  233. {
  234. struct phy_device *phydev;
  235. struct mii_dev *bus;
  236. int ret;
  237. setup_iomux_enet();
  238. iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
  239. ret = enable_fec_anatop_clock(0, ENET_125MHZ);
  240. if (ret)
  241. return ret;
  242. setup_mac_from_fuse();
  243. bus = fec_get_miibus(IMX_FEC_BASE, -1);
  244. if (!bus)
  245. return -ENODEV;
  246. /*
  247. * We use here the "rgmii-id" mode of operation and allow M88E1512
  248. * PHY to use its internally callibrated RX/TX delays
  249. */
  250. phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */,
  251. PHY_INTERFACE_MODE_RGMII_ID);
  252. if (!phydev) {
  253. ret = -ENODEV;
  254. goto err_phy;
  255. }
  256. /* display5 due to PCB routing can only work with 100 Mbps */
  257. phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
  258. ADVERTISED_1000baseX_Full |
  259. SUPPORTED_1000baseT_Half |
  260. SUPPORTED_1000baseT_Full);
  261. ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev);
  262. if (ret)
  263. goto err_sw;
  264. return 0;
  265. err_sw:
  266. free(phydev);
  267. err_phy:
  268. mdio_unregister(bus);
  269. free(bus);
  270. return ret;
  271. }
  272. #endif /* CONFIG_FEC_MXC */
  273. /*
  274. * Do not overwrite the console
  275. * Always use serial for U-Boot console
  276. */
  277. int overwrite_console(void)
  278. {
  279. return 1;
  280. }
  281. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  282. int ft_board_setup(void *blob, bd_t *bd)
  283. {
  284. fdt_fixup_ethernet(blob);
  285. return 0;
  286. }
  287. #endif
  288. int board_init(void)
  289. {
  290. debug("board init\n");
  291. /* address of boot parameters */
  292. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  293. /* Setup iomux for non console UARTS */
  294. displ5_set_iomux_uart();
  295. displ5_setup_ecspi();
  296. SETUP_IOMUX_PADS(misc_pads);
  297. get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0],
  298. ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id);
  299. debug("SWx unit_id 0x%x\n", unit_id);
  300. get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0],
  301. ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id);
  302. debug("HWx cpu_id 0x%x\n", cpu_id);
  303. if (hw_ids_valid && sw_ids_valid)
  304. printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
  305. udelay(25);
  306. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  307. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  308. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  309. return 0;
  310. }
  311. #ifdef CONFIG_CMD_BMODE
  312. static const struct boot_mode board_boot_modes[] = {
  313. /* eMMC, USDHC-4, 8-bit bus width */
  314. /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */
  315. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  316. {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
  317. {NULL, 0},
  318. };
  319. static void setup_boot_modes(void)
  320. {
  321. add_board_boot_modes(board_boot_modes);
  322. }
  323. #else
  324. static inline void setup_boot_modes(void) {}
  325. #endif
  326. int misc_init_r(void)
  327. {
  328. int ret;
  329. setup_boot_modes();
  330. ret = gpio_request(EM_PAD, "Emergency_PAD");
  331. if (ret) {
  332. printf("Can't request emergency PAD gpio\n");
  333. return ret;
  334. }
  335. ret = gpio_direction_input(EM_PAD);
  336. if (ret) {
  337. printf("Can't set emergency PAD direction\n");
  338. return ret;
  339. }
  340. return 0;
  341. }