wb50n.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. */
  4. #include <common.h>
  5. #include <asm/io.h>
  6. #include <asm/arch/sama5_sfr.h>
  7. #include <asm/arch/sama5d3_smc.h>
  8. #include <asm/arch/at91_common.h>
  9. #include <asm/arch/at91_pmc.h>
  10. #include <asm/arch/at91_rstc.h>
  11. #include <asm/arch/gpio.h>
  12. #include <asm/arch/clk.h>
  13. #include <env.h>
  14. #include <micrel.h>
  15. #include <net.h>
  16. #include <netdev.h>
  17. #include <spl.h>
  18. #include <asm/arch/atmel_mpddrc.h>
  19. #include <asm/arch/at91_wdt.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /* ------------------------------------------------------------------------- */
  22. /*
  23. * Miscelaneous platform dependent initialisations
  24. */
  25. void wb50n_nand_hw_init(void)
  26. {
  27. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  28. at91_periph_clk_enable(ATMEL_ID_SMC);
  29. /* Configure SMC CS3 for NAND/SmartMedia */
  30. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  31. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  32. &smc->cs[3].setup);
  33. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  34. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  35. &smc->cs[3].pulse);
  36. writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  37. &smc->cs[3].cycle);
  38. writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  39. AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
  40. AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) |
  41. AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  42. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  43. AT91_SMC_MODE_EXNW_DISABLE |
  44. AT91_SMC_MODE_DBW_8 |
  45. AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode);
  46. /* Disable Flash Write Protect Line */
  47. at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
  48. }
  49. int board_early_init_f(void)
  50. {
  51. at91_periph_clk_enable(ATMEL_ID_PIOA);
  52. at91_periph_clk_enable(ATMEL_ID_PIOB);
  53. at91_periph_clk_enable(ATMEL_ID_PIOC);
  54. at91_periph_clk_enable(ATMEL_ID_PIOD);
  55. at91_periph_clk_enable(ATMEL_ID_PIOE);
  56. at91_seriald_hw_init();
  57. return 0;
  58. }
  59. int board_init(void)
  60. {
  61. /* adress of boot parameters */
  62. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  63. wb50n_nand_hw_init();
  64. at91_macb_hw_init();
  65. return 0;
  66. }
  67. int dram_init(void)
  68. {
  69. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  70. CONFIG_SYS_SDRAM_SIZE);
  71. return 0;
  72. }
  73. int board_phy_config(struct phy_device *phydev)
  74. {
  75. /* rx data delay */
  76. ksz9021_phy_extended_write(phydev,
  77. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
  78. /* tx data delay */
  79. ksz9021_phy_extended_write(phydev,
  80. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
  81. /* rx/tx clock delay */
  82. ksz9021_phy_extended_write(phydev,
  83. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
  84. return 0;
  85. }
  86. int board_eth_init(bd_t *bis)
  87. {
  88. int rc = 0;
  89. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
  90. return rc;
  91. }
  92. #ifdef CONFIG_BOARD_LATE_INIT
  93. #include <linux/ctype.h>
  94. int board_late_init(void)
  95. {
  96. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  97. const char *LAIRD_NAME = "lrd_name";
  98. char name[32], *p;
  99. strcpy(name, get_cpu_name());
  100. for (p = name; *p != '\0'; *p = tolower(*p), p++)
  101. ;
  102. strcat(name, "-wb50n");
  103. env_set(LAIRD_NAME, name);
  104. #endif
  105. return 0;
  106. }
  107. #endif
  108. /* SPL */
  109. #ifdef CONFIG_SPL_BUILD
  110. void spl_board_init(void)
  111. {
  112. wb50n_nand_hw_init();
  113. }
  114. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  115. {
  116. ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
  117. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
  118. ATMEL_MPDDRC_CR_NR_ROW_13 |
  119. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  120. ATMEL_MPDDRC_CR_NDQS_DISABLED |
  121. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  122. ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
  123. ddr2->rtr = 0x411;
  124. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  125. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  126. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  127. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  128. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  129. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  130. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  131. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  132. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  133. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  134. 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  135. 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  136. ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
  137. 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  138. 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  139. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  140. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  141. }
  142. void mem_init(void)
  143. {
  144. struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
  145. struct atmel_mpddrc_config ddr2;
  146. ddr2_conf(&ddr2);
  147. writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN,
  148. &sfr->ddrcfg);
  149. /* enable MPDDR clock */
  150. at91_periph_clk_enable(ATMEL_ID_MPDDRC);
  151. at91_system_clk_enable(AT91_PMC_DDR);
  152. /* DDRAM2 Controller initialize */
  153. ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
  154. }
  155. void at91_pmc_init(void)
  156. {
  157. u32 tmp;
  158. tmp = AT91_PMC_PLLAR_29 |
  159. AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
  160. AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1);
  161. at91_plla_init(tmp);
  162. at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
  163. tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA;
  164. at91_mck_init(tmp);
  165. }
  166. #endif