video.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Novena video output support
  4. *
  5. * IT6251 code based on code Copyright (C) 2014 Sean Cross
  6. * from https://github.com/xobs/novena-linux.git commit
  7. * 3d85836ee1377d445531928361809612aa0a18db
  8. *
  9. * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  10. */
  11. #include <common.h>
  12. #include <linux/errno.h>
  13. #include <asm/gpio.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/crm_regs.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include <asm/arch/iomux.h>
  19. #include <asm/arch/mxc_hdmi.h>
  20. #include <asm/arch/sys_proto.h>
  21. #include <asm/mach-imx/iomux-v3.h>
  22. #include <asm/mach-imx/mxc_i2c.h>
  23. #include <asm/mach-imx/video.h>
  24. #include <i2c.h>
  25. #include <input.h>
  26. #include <ipu_pixfmt.h>
  27. #include <linux/fb.h>
  28. #include <linux/input.h>
  29. #include <malloc.h>
  30. #include <stdio_dev.h>
  31. #include "novena.h"
  32. #define IT6251_VENDOR_ID_LOW 0x00
  33. #define IT6251_VENDOR_ID_HIGH 0x01
  34. #define IT6251_DEVICE_ID_LOW 0x02
  35. #define IT6251_DEVICE_ID_HIGH 0x03
  36. #define IT6251_SYSTEM_STATUS 0x0d
  37. #define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0)
  38. #define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1)
  39. #define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2)
  40. #define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3)
  41. #define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4)
  42. #define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5)
  43. #define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6)
  44. #define IT6251_REF_STATE 0x0e
  45. #define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0)
  46. #define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1)
  47. #define IT6251_REF_STATE_CR_PATTERN (1 << 2)
  48. #define IT6251_REF_STATE_EQ_PATTERN (1 << 3)
  49. #define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4)
  50. #define IT6251_REF_STATE_MUTED (1 << 5)
  51. #define IT6251_REG_PCLK_CNT_LOW 0x57
  52. #define IT6251_REG_PCLK_CNT_HIGH 0x58
  53. #define IT6521_RETRY_MAX 20
  54. static int it6251_is_stable(void)
  55. {
  56. const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
  57. const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
  58. int status;
  59. int clkcnt;
  60. int rpclkcnt;
  61. int refstate;
  62. rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
  63. ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
  64. debug("RPCLKCnt: %d\n", rpclkcnt);
  65. status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
  66. debug("System status: 0x%02x\n", status);
  67. clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
  68. ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
  69. 0x0f00);
  70. debug("Clock: 0x%02x\n", clkcnt);
  71. refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
  72. debug("Ref Link State: 0x%02x\n", refstate);
  73. if ((refstate & 0x1f) != 0)
  74. return 0;
  75. /* If video is muted, that's a failure */
  76. if (refstate & IT6251_REF_STATE_MUTED)
  77. return 0;
  78. if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
  79. return 0;
  80. return 1;
  81. }
  82. static int it6251_ready(void)
  83. {
  84. const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
  85. /* Test if the IT6251 came out of reset by reading ID regs. */
  86. if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
  87. return 0;
  88. if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
  89. return 0;
  90. if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
  91. return 0;
  92. if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
  93. return 0;
  94. return 1;
  95. }
  96. static void it6251_program_regs(void)
  97. {
  98. const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
  99. const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
  100. i2c_reg_write(caddr, 0x05, 0x00);
  101. mdelay(1);
  102. /* set LVDSRX address, and enable */
  103. i2c_reg_write(caddr, 0xfd, 0xbc);
  104. i2c_reg_write(caddr, 0xfe, 0x01);
  105. /*
  106. * LVDSRX
  107. */
  108. /* This write always fails, because the chip goes into reset */
  109. /* reset LVDSRX */
  110. i2c_reg_write(laddr, 0x05, 0xff);
  111. i2c_reg_write(laddr, 0x05, 0x00);
  112. /* reset LVDSRX PLL */
  113. i2c_reg_write(laddr, 0x3b, 0x42);
  114. i2c_reg_write(laddr, 0x3b, 0x43);
  115. /* something with SSC PLL */
  116. i2c_reg_write(laddr, 0x3c, 0x08);
  117. /* don't swap links, but writing reserved registers */
  118. i2c_reg_write(laddr, 0x0b, 0x88);
  119. /* JEIDA, 8-bit depth 0x11, orig 0x42 */
  120. i2c_reg_write(laddr, 0x2c, 0x01);
  121. /* "reserved" */
  122. i2c_reg_write(laddr, 0x32, 0x04);
  123. /* "reserved" */
  124. i2c_reg_write(laddr, 0x35, 0xe0);
  125. /* "reserved" + clock delay */
  126. i2c_reg_write(laddr, 0x2b, 0x24);
  127. /* reset LVDSRX pix clock */
  128. i2c_reg_write(laddr, 0x05, 0x02);
  129. i2c_reg_write(laddr, 0x05, 0x00);
  130. /*
  131. * DPTX
  132. */
  133. /* set for two lane mode, normal op, no swapping, no downspread */
  134. i2c_reg_write(caddr, 0x16, 0x02);
  135. /* some AUX channel EDID magic */
  136. i2c_reg_write(caddr, 0x23, 0x40);
  137. /* power down lanes 3-0 */
  138. i2c_reg_write(caddr, 0x5c, 0xf3);
  139. /* enable DP scrambling, change EQ CR phase */
  140. i2c_reg_write(caddr, 0x5f, 0x06);
  141. /* color mode RGB, pclk/2 */
  142. i2c_reg_write(caddr, 0x60, 0x02);
  143. /* dual pixel input mode, no EO swap, no RGB swap */
  144. i2c_reg_write(caddr, 0x61, 0x04);
  145. /* M444B24 video format */
  146. i2c_reg_write(caddr, 0x62, 0x01);
  147. /* vesa range / not interlace / vsync high / hsync high */
  148. i2c_reg_write(caddr, 0xa0, 0x0F);
  149. /* hpd event timer set to 1.6-ish ms */
  150. i2c_reg_write(caddr, 0xc9, 0xf5);
  151. /* more reserved magic */
  152. i2c_reg_write(caddr, 0xca, 0x4d);
  153. i2c_reg_write(caddr, 0xcb, 0x37);
  154. /* enhanced framing mode, auto video fifo reset, video mute disable */
  155. i2c_reg_write(caddr, 0xd3, 0x03);
  156. /* "vidstmp" and some reserved stuff */
  157. i2c_reg_write(caddr, 0xd4, 0x45);
  158. /* queue number -- reserved */
  159. i2c_reg_write(caddr, 0xe7, 0xa0);
  160. /* info frame packets and reserved */
  161. i2c_reg_write(caddr, 0xe8, 0x33);
  162. /* more AVI stuff */
  163. i2c_reg_write(caddr, 0xec, 0x00);
  164. /* select PC master reg for aux channel? */
  165. i2c_reg_write(caddr, 0x23, 0x42);
  166. /* send PC request commands */
  167. i2c_reg_write(caddr, 0x24, 0x00);
  168. i2c_reg_write(caddr, 0x25, 0x00);
  169. i2c_reg_write(caddr, 0x26, 0x00);
  170. /* native aux read */
  171. i2c_reg_write(caddr, 0x2b, 0x00);
  172. /* back to internal */
  173. i2c_reg_write(caddr, 0x23, 0x40);
  174. /* voltage swing level 3 */
  175. i2c_reg_write(caddr, 0x19, 0xff);
  176. /* pre-emphasis level 3 */
  177. i2c_reg_write(caddr, 0x1a, 0xff);
  178. /* start link training */
  179. i2c_reg_write(caddr, 0x17, 0x01);
  180. }
  181. static int it6251_init(void)
  182. {
  183. const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
  184. int reg;
  185. int tries, retries = 0;
  186. for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
  187. /* Program the chip. */
  188. it6251_program_regs();
  189. /* Wait for video stable. */
  190. for (tries = 0; tries < 100; tries++) {
  191. reg = i2c_reg_read(caddr, 0x17);
  192. /* Test Link CFG, STS, LCS read done. */
  193. if ((reg & 0xe0) != 0xe0) {
  194. /* Not yet, wait a bit more. */
  195. mdelay(2);
  196. continue;
  197. }
  198. /* Test if the video input is stable. */
  199. if (it6251_is_stable())
  200. return 0;
  201. }
  202. /*
  203. * If we couldn't stabilize, requeue and try again,
  204. * because it means that the LVDS channel isn't
  205. * stable yet.
  206. */
  207. printf("Display didn't stabilize.\n");
  208. printf("This may be because the LVDS port is still in powersave mode.\n");
  209. mdelay(50);
  210. }
  211. return -EINVAL;
  212. }
  213. static void enable_hdmi(struct display_info_t const *dev)
  214. {
  215. imx_enable_hdmi_phy();
  216. }
  217. static int lvds_enabled;
  218. static void enable_lvds(struct display_info_t const *dev)
  219. {
  220. if (lvds_enabled)
  221. return;
  222. /* ITE IT6251 power enable. */
  223. gpio_request(NOVENA_ITE6251_PWR_GPIO, "ite6251-power");
  224. gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
  225. mdelay(10);
  226. gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
  227. mdelay(20);
  228. lvds_enabled = 1;
  229. }
  230. static int detect_lvds(struct display_info_t const *dev)
  231. {
  232. int ret, loops = 250;
  233. enable_lvds(dev);
  234. ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
  235. if (ret) {
  236. puts("Cannot select IT6251 I2C bus.\n");
  237. return 0;
  238. }
  239. /* Wait up-to ~250 mS for the LVDS to come up. */
  240. while (--loops) {
  241. ret = it6251_ready();
  242. if (ret)
  243. return ret;
  244. mdelay(1);
  245. }
  246. return 0;
  247. }
  248. struct display_info_t const displays[] = {
  249. {
  250. /* HDMI Output */
  251. .bus = -1,
  252. .addr = 0,
  253. .pixfmt = IPU_PIX_FMT_RGB24,
  254. .detect = detect_hdmi,
  255. .enable = enable_hdmi,
  256. .mode = {
  257. .name = "HDMI",
  258. .refresh = 60,
  259. .xres = 1024,
  260. .yres = 768,
  261. .pixclock = 15384,
  262. .left_margin = 220,
  263. .right_margin = 40,
  264. .upper_margin = 21,
  265. .lower_margin = 7,
  266. .hsync_len = 60,
  267. .vsync_len = 10,
  268. .sync = FB_SYNC_EXT,
  269. .vmode = FB_VMODE_NONINTERLACED
  270. },
  271. }, {
  272. /* LVDS Output: N133HSE-EA1 Rev. C1 */
  273. .bus = -1,
  274. .pixfmt = IPU_PIX_FMT_RGB24,
  275. .detect = detect_lvds,
  276. .enable = enable_lvds,
  277. .mode = {
  278. .name = "Chimei-FHD",
  279. .refresh = 60,
  280. .xres = 1920,
  281. .yres = 1080,
  282. .pixclock = 15384,
  283. .left_margin = 148,
  284. .right_margin = 88,
  285. .upper_margin = 36,
  286. .lower_margin = 4,
  287. .hsync_len = 44,
  288. .vsync_len = 5,
  289. .sync = FB_SYNC_HOR_HIGH_ACT |
  290. FB_SYNC_VERT_HIGH_ACT |
  291. FB_SYNC_EXT,
  292. .vmode = FB_VMODE_NONINTERLACED,
  293. },
  294. },
  295. };
  296. size_t display_count = ARRAY_SIZE(displays);
  297. static void enable_vpll(void)
  298. {
  299. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  300. int timeout = 100000;
  301. setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
  302. clrsetbits_le32(&ccm->analog_pll_video,
  303. BM_ANADIG_PLL_VIDEO_DIV_SELECT |
  304. BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
  305. BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
  306. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
  307. writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
  308. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
  309. clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
  310. while (timeout--)
  311. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  312. break;
  313. if (timeout < 0)
  314. printf("Warning: video pll lock timeout!\n");
  315. clrsetbits_le32(&ccm->analog_pll_video,
  316. BM_ANADIG_PLL_VIDEO_BYPASS,
  317. BM_ANADIG_PLL_VIDEO_ENABLE);
  318. }
  319. void setup_display_clock(void)
  320. {
  321. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  322. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  323. enable_ipu_clock();
  324. enable_vpll();
  325. imx_setup_hdmi();
  326. /* Turn on IPU LDB DI0 clocks */
  327. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  328. /* Switch LDB DI0 to PLL5 (Video PLL) */
  329. clrsetbits_le32(&mxc_ccm->cs2cdr,
  330. MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
  331. (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  332. /* LDB clock div by 3.5 */
  333. clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  334. /* DI0 clock derived from ldb_di0_clk */
  335. clrsetbits_le32(&mxc_ccm->chsccdr,
  336. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
  337. (CHSCCDR_CLK_SEL_LDB_DI0 <<
  338. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
  339. );
  340. /* Enable both LVDS channels, both connected to DI0. */
  341. writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
  342. IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
  343. IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
  344. IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
  345. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
  346. IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
  347. IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
  348. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
  349. &iomux->gpr[2]);
  350. clrsetbits_le32(&iomux->gpr[3],
  351. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  352. IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
  353. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  354. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
  355. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  356. IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
  357. );
  358. }
  359. void setup_display_lvds(void)
  360. {
  361. int ret;
  362. ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
  363. if (ret) {
  364. puts("Cannot select LVDS-to-eDP I2C bus.\n");
  365. return;
  366. }
  367. /* The IT6251 should be ready now, if it's not, it's not connected. */
  368. ret = it6251_ready();
  369. if (!ret)
  370. return;
  371. /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
  372. ret = it6251_init();
  373. if (!ret) {
  374. gpio_request(NOVENA_BACKLIGHT_PWR_GPIO, "backlight-power");
  375. gpio_request(NOVENA_BACKLIGHT_PWM_GPIO, "backlight-pwm");
  376. /* Backlight power enable. */
  377. gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
  378. /* PWM backlight pin, always on for full brightness. */
  379. gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
  380. }
  381. }