kmp204x.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Keymile AG
  4. * Valentin Longchamp <valentin.longchamp@keymile.com>
  5. *
  6. * Copyright 2011,2012 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <env.h>
  11. #include <netdev.h>
  12. #include <linux/compiler.h>
  13. #include <asm/mmu.h>
  14. #include <asm/processor.h>
  15. #include <asm/cache.h>
  16. #include <asm/immap_85xx.h>
  17. #include <asm/fsl_law.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_portals.h>
  20. #include <asm/fsl_liodn.h>
  21. #include <fm_eth.h>
  22. #include "../common/common.h"
  23. #include "kmp204x.h"
  24. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  25. int checkboard(void)
  26. {
  27. printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
  28. return 0;
  29. }
  30. /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
  31. * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
  32. * For I2C only the low state is activly driven and high state is pulled-up
  33. * by a resistor. Therefore the deblock GPIOs are used
  34. * -> as an active output to drive a low state
  35. * -> as an open-drain input to have a pulled-up high state
  36. */
  37. /* QRIO GPIOs used for deblocking */
  38. #define DEBLOCK_PORT1 GPIO_A
  39. #define DEBLOCK_SCL1 20
  40. #define DEBLOCK_SDA1 21
  41. /* By default deblock GPIOs are floating */
  42. static void i2c_deblock_gpio_cfg(void)
  43. {
  44. /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
  45. qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
  46. qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
  47. qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
  48. qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
  49. }
  50. void set_sda(int state)
  51. {
  52. qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
  53. }
  54. void set_scl(int state)
  55. {
  56. qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
  57. }
  58. int get_sda(void)
  59. {
  60. return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
  61. }
  62. int get_scl(void)
  63. {
  64. return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
  65. }
  66. #define ZL30158_RST 8
  67. #define BFTIC4_RST 0
  68. #define RSTRQSR1_WDT_RR 0x00200000
  69. #define RSTRQSR1_SW_RR 0x00100000
  70. int board_early_init_f(void)
  71. {
  72. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  73. bool cpuwd_flag = false;
  74. /* configure mode for uP reset request */
  75. qrio_uprstreq(UPREQ_CORE_RST);
  76. /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
  77. setbits_be32(&gur->ddrclkdr, 0x001f000f);
  78. /* set reset reason according CPU register */
  79. if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
  80. RSTRQSR1_WDT_RR)
  81. cpuwd_flag = true;
  82. qrio_cpuwd_flag(cpuwd_flag);
  83. /* clear CPU bits by writing 1 */
  84. setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
  85. /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
  86. qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
  87. /* and enable WD on it */
  88. qrio_wdmask(BFTIC4_RST, true);
  89. /* set the ZL30138's prstcfg to reset at power-up only */
  90. qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
  91. /* and take it out of reset as soon as possible (needed for Hooper) */
  92. qrio_prst(ZL30158_RST, false, false);
  93. return 0;
  94. }
  95. int board_early_init_r(void)
  96. {
  97. int ret = 0;
  98. /* Flush d-cache and invalidate i-cache of any FLASH data */
  99. flush_dcache();
  100. invalidate_icache();
  101. set_liodns();
  102. setup_qbman_portals();
  103. ret = trigger_fpga_config();
  104. if (ret)
  105. printf("error triggering PCIe FPGA config\n");
  106. /* enable the Unit LED (red) & Boot LED (on) */
  107. qrio_set_leds();
  108. /* enable Application Buffer */
  109. qrio_enable_app_buffer();
  110. return ret;
  111. }
  112. unsigned long get_board_sys_clk(unsigned long dummy)
  113. {
  114. return 66666666;
  115. }
  116. #define ETH_FRONT_PHY_RST 15
  117. #define QSFP2_RST 11
  118. #define QSFP1_RST 10
  119. #define ZL30343_RST 9
  120. int misc_init_f(void)
  121. {
  122. /* configure QRIO pis for i2c deblocking */
  123. i2c_deblock_gpio_cfg();
  124. /* configure the front phy's prstcfg and take it out of reset */
  125. qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  126. qrio_prst(ETH_FRONT_PHY_RST, false, false);
  127. /* set the ZL30343 prstcfg to reset at power-up only */
  128. qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
  129. /* and enable the WD on it */
  130. qrio_wdmask(ZL30343_RST, true);
  131. /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
  132. qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
  133. qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
  134. /* and enable the WD on them */
  135. qrio_wdmask(QSFP1_RST, true);
  136. qrio_wdmask(QSFP2_RST, true);
  137. return 0;
  138. }
  139. #define NUM_SRDS_BANKS 2
  140. int misc_init_r(void)
  141. {
  142. serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  143. u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
  144. SRDS_PLLCR0_RFCK_SEL_125};
  145. unsigned int i;
  146. /* check SERDES reference clocks */
  147. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  148. u32 actual = in_be32(&regs->bank[i].pllcr0);
  149. actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
  150. if (actual != expected[i]) {
  151. printf("Warning: SERDES bank %u expects reference \
  152. clock %sMHz, but actual is %sMHz\n", i + 1,
  153. serdes_clock_to_string(expected[i]),
  154. serdes_clock_to_string(actual));
  155. }
  156. }
  157. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  158. return 0;
  159. }
  160. #if defined(CONFIG_HUSH_INIT_VAR)
  161. int hush_init_var(void)
  162. {
  163. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  164. return 0;
  165. }
  166. #endif
  167. #if defined(CONFIG_LAST_STAGE_INIT)
  168. int last_stage_init(void)
  169. {
  170. #if defined(CONFIG_KMCOGE4)
  171. /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
  172. struct bfticu_iomap *bftic4 =
  173. (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
  174. u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
  175. if (dip_switch != 0) {
  176. /* start bootloader */
  177. puts("DIP: Enabled\n");
  178. env_set("actual_bank", "0");
  179. }
  180. #endif
  181. set_km_env();
  182. return 0;
  183. }
  184. #endif
  185. #ifdef CONFIG_SYS_DPAA_FMAN
  186. void fdt_fixup_fman_mac_addresses(void *blob)
  187. {
  188. int node, i, ret;
  189. char *tmp, *end;
  190. unsigned char mac_addr[6];
  191. /* get the mac addr from env */
  192. tmp = env_get("ethaddr");
  193. if (!tmp) {
  194. printf("ethaddr env variable not defined\n");
  195. return;
  196. }
  197. for (i = 0; i < 6; i++) {
  198. mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
  199. if (tmp)
  200. tmp = (*end) ? end+1 : end;
  201. }
  202. /* find the correct fdt ethernet path and correct it */
  203. node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
  204. if (node < 0) {
  205. printf("no /soc/fman/ethernet path offset\n");
  206. return;
  207. }
  208. ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
  209. if (ret) {
  210. printf("error setting local-mac-address property\n");
  211. return;
  212. }
  213. }
  214. #endif
  215. int ft_board_setup(void *blob, bd_t *bd)
  216. {
  217. phys_addr_t base;
  218. phys_size_t size;
  219. ft_cpu_setup(blob, bd);
  220. base = env_get_bootm_low();
  221. size = env_get_bootm_size();
  222. fdt_fixup_memory(blob, (u64)base, (u64)size);
  223. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  224. fsl_fdt_fixup_dr_usb(blob, bd);
  225. #endif
  226. #ifdef CONFIG_PCI
  227. pci_of_setup(blob, bd);
  228. #endif
  229. fdt_fixup_liodn(blob);
  230. #ifdef CONFIG_SYS_DPAA_FMAN
  231. fdt_fixup_fman_ethernet(blob);
  232. fdt_fixup_fman_mac_addresses(blob);
  233. #endif
  234. return 0;
  235. }
  236. #if defined(CONFIG_POST)
  237. /* DIC26_SELFTEST GPIO used to start factory test sw */
  238. #define SELFTEST_PORT GPIO_A
  239. #define SELFTEST_PIN 31
  240. int post_hotkeys_pressed(void)
  241. {
  242. qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
  243. return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
  244. }
  245. #endif