km_arm.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Prafulla Wadaskar <prafulla@marvell.com>
  6. *
  7. * (C) Copyright 2009
  8. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  9. *
  10. * (C) Copyright 2010
  11. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  12. */
  13. #include <common.h>
  14. #include <env.h>
  15. #include <i2c.h>
  16. #include <nand.h>
  17. #include <netdev.h>
  18. #include <miiphy.h>
  19. #include <spi.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/cpu.h>
  22. #include <asm/arch/soc.h>
  23. #include <asm/arch/mpp.h>
  24. #include "../common/common.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. /*
  27. * BOCO FPGA definitions
  28. */
  29. #define BOCO 0x10
  30. #define REG_CTRL_H 0x02
  31. #define MASK_WRL_UNITRUN 0x01
  32. #define MASK_RBX_PGY_PRESENT 0x40
  33. #define REG_IRQ_CIRQ2 0x2d
  34. #define MASK_RBI_DEFECT_16 0x01
  35. /*
  36. * PHY registers definitions
  37. */
  38. #define PHY_MARVELL_OUI 0x5043
  39. #define PHY_MARVELL_88E1118_MODEL 0x0022
  40. #define PHY_MARVELL_88E1118R_MODEL 0x0024
  41. #define PHY_MARVELL_PAGE_REG 0x0016
  42. #define PHY_MARVELL_DEFAULT_PAGE 0x0000
  43. #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003
  44. #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
  45. #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000
  46. #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0)
  47. #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4)
  48. #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8)
  49. /* I/O pin to erase flash RGPP09 = MPP43 */
  50. #define KM_FLASH_ERASE_ENABLE 43
  51. /* Multi-Purpose Pins Functionality configuration */
  52. static const u32 kwmpp_config[] = {
  53. MPP0_NF_IO2,
  54. MPP1_NF_IO3,
  55. MPP2_NF_IO4,
  56. MPP3_NF_IO5,
  57. MPP4_NF_IO6,
  58. MPP5_NF_IO7,
  59. MPP6_SYSRST_OUTn,
  60. #if defined(KM_PCIE_RESET_MPP7)
  61. MPP7_GPO,
  62. #else
  63. MPP7_PEX_RST_OUTn,
  64. #endif
  65. #if defined(CONFIG_SYS_I2C_SOFT)
  66. MPP8_GPIO, /* SDA */
  67. MPP9_GPIO, /* SCL */
  68. #endif
  69. MPP10_UART0_TXD,
  70. MPP11_UART0_RXD,
  71. MPP12_GPO, /* Reserved */
  72. MPP13_UART1_TXD,
  73. MPP14_UART1_RXD,
  74. MPP15_GPIO, /* Not used */
  75. MPP16_GPIO, /* Not used */
  76. MPP17_GPIO, /* Reserved */
  77. MPP18_NF_IO0,
  78. MPP19_NF_IO1,
  79. MPP20_GPIO,
  80. MPP21_GPIO,
  81. MPP22_GPIO,
  82. MPP23_GPIO,
  83. MPP24_GPIO,
  84. MPP25_GPIO,
  85. MPP26_GPIO,
  86. MPP27_GPIO,
  87. MPP28_GPIO,
  88. MPP29_GPIO,
  89. MPP30_GPIO,
  90. MPP31_GPIO,
  91. MPP32_GPIO,
  92. MPP33_GPIO,
  93. MPP34_GPIO, /* CDL1 (input) */
  94. MPP35_GPIO, /* CDL2 (input) */
  95. MPP36_GPIO, /* MAIN_IRQ (input) */
  96. MPP37_GPIO, /* BOARD_LED */
  97. MPP38_GPIO, /* Piggy3 LED[1] */
  98. MPP39_GPIO, /* Piggy3 LED[2] */
  99. MPP40_GPIO, /* Piggy3 LED[3] */
  100. MPP41_GPIO, /* Piggy3 LED[4] */
  101. MPP42_GPIO, /* Piggy3 LED[5] */
  102. MPP43_GPIO, /* Piggy3 LED[6] */
  103. MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
  104. MPP45_GPIO, /* Piggy3 LED[8] */
  105. MPP46_GPIO, /* Reserved */
  106. MPP47_GPIO, /* Reserved */
  107. MPP48_GPIO, /* Reserved */
  108. MPP49_GPIO, /* SW_INTOUTn */
  109. 0
  110. };
  111. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  112. #if defined(CONFIG_KM_MGCOGE3UN)
  113. /*
  114. * Wait for startup OK from mgcoge3ne
  115. */
  116. static int startup_allowed(void)
  117. {
  118. unsigned char buf;
  119. /*
  120. * Read CIRQ16 bit (bit 0)
  121. */
  122. if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
  123. printf("%s: Error reading Boco\n", __func__);
  124. else
  125. if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
  126. return 1;
  127. return 0;
  128. }
  129. #endif
  130. #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
  131. /*
  132. * All boards with PIGGY4 connected via a simple switch have ethernet always
  133. * present.
  134. */
  135. int ethernet_present(void)
  136. {
  137. return 1;
  138. }
  139. #else
  140. int ethernet_present(void)
  141. {
  142. uchar buf;
  143. int ret = 0;
  144. if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
  145. printf("%s: Error reading Boco\n", __func__);
  146. return -1;
  147. }
  148. if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
  149. ret = 1;
  150. return ret;
  151. }
  152. #endif
  153. static int initialize_unit_leds(void)
  154. {
  155. /*
  156. * Init the unit LEDs per default they all are
  157. * ok apart from bootstat
  158. */
  159. uchar buf;
  160. if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
  161. printf("%s: Error reading Boco\n", __func__);
  162. return -1;
  163. }
  164. buf |= MASK_WRL_UNITRUN;
  165. if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
  166. printf("%s: Error writing Boco\n", __func__);
  167. return -1;
  168. }
  169. return 0;
  170. }
  171. static void set_bootcount_addr(void)
  172. {
  173. uchar buf[32];
  174. unsigned int bootcountaddr;
  175. bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
  176. sprintf((char *)buf, "0x%x", bootcountaddr);
  177. env_set("bootcountaddr", (char *)buf);
  178. }
  179. int misc_init_r(void)
  180. {
  181. #if defined(CONFIG_KM_MGCOGE3UN)
  182. char *wait_for_ne;
  183. u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
  184. wait_for_ne = env_get("waitforne");
  185. if ((wait_for_ne != NULL) && (dip_switch == 0)) {
  186. if (strcmp(wait_for_ne, "true") == 0) {
  187. int cnt = 0;
  188. int abort = 0;
  189. puts("NE go: ");
  190. while (startup_allowed() == 0) {
  191. if (tstc()) {
  192. (void) getc(); /* consume input */
  193. abort = 1;
  194. break;
  195. }
  196. udelay(200000);
  197. cnt++;
  198. if (cnt == 5)
  199. puts("wait\b\b\b\b");
  200. if (cnt == 10) {
  201. cnt = 0;
  202. puts(" \b\b\b\b");
  203. }
  204. }
  205. if (abort == 1)
  206. printf("\nAbort waiting for ne\n");
  207. else
  208. puts("OK\n");
  209. }
  210. }
  211. #endif
  212. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  213. initialize_unit_leds();
  214. set_km_env();
  215. set_bootcount_addr();
  216. return 0;
  217. }
  218. int board_early_init_f(void)
  219. {
  220. #if defined(CONFIG_SYS_I2C_SOFT)
  221. u32 tmp;
  222. /* set the 2 bitbang i2c pins as output gpios */
  223. tmp = readl(MVEBU_GPIO0_BASE + 4);
  224. writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
  225. #endif
  226. /* adjust SDRAM size for bank 0 */
  227. mvebu_sdram_size_adjust(0);
  228. kirkwood_mpp_conf(kwmpp_config, NULL);
  229. return 0;
  230. }
  231. int board_init(void)
  232. {
  233. /* address of boot parameters */
  234. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  235. /*
  236. * The KM_FLASH_GPIO_PIN switches between using a
  237. * NAND or a SPI FLASH. Set this pin on start
  238. * to NAND mode.
  239. */
  240. kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
  241. kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
  242. #if defined(CONFIG_SYS_I2C_SOFT)
  243. /*
  244. * Reinit the GPIO for I2C Bitbang driver so that the now
  245. * available gpio framework is consistent. The calls to
  246. * direction output in are not necessary, they are already done in
  247. * board_early_init_f
  248. */
  249. kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
  250. kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
  251. #endif
  252. #if defined(CONFIG_SYS_EEPROM_WREN)
  253. kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
  254. kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
  255. #endif
  256. #if defined(CONFIG_KM_FPGA_CONFIG)
  257. trigger_fpga_config();
  258. #endif
  259. return 0;
  260. }
  261. int board_late_init(void)
  262. {
  263. #if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN))
  264. u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
  265. /* if pin 1 do full erase */
  266. if (dip_switch != 0) {
  267. /* start bootloader */
  268. puts("DIP: Enabled\n");
  269. env_set("actual_bank", "0");
  270. }
  271. #endif
  272. #if defined(CONFIG_KM_FPGA_CONFIG)
  273. wait_for_fpga_config();
  274. fpga_reset();
  275. toggle_eeprom_spi_bus();
  276. #endif
  277. return 0;
  278. }
  279. static const u32 spi_mpp_config[] = {
  280. MPP1_SPI_MOSI,
  281. MPP2_SPI_SCK,
  282. MPP3_SPI_MISO,
  283. 0
  284. };
  285. static u32 spi_mpp_backup[4];
  286. int mvebu_board_spi_claim_bus(struct udevice *dev)
  287. {
  288. spi_mpp_backup[3] = 0;
  289. /* set new spi mpp config and save current one */
  290. kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
  291. kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
  292. return 0;
  293. }
  294. int mvebu_board_spi_release_bus(struct udevice *dev)
  295. {
  296. /* restore saved mpp config */
  297. kirkwood_mpp_conf(spi_mpp_backup, NULL);
  298. kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
  299. return 0;
  300. }
  301. #if (defined(CONFIG_KM_PIGGY4_88E6061))
  302. #define PHY_LED_SEL_REG 0x18
  303. #define PHY_LED0_LINK (0x5)
  304. #define PHY_LED1_ACT (0x8<<4)
  305. #define PHY_LED2_INT (0xe<<8)
  306. #define PHY_SPEC_CTRL_REG 0x1c
  307. #define PHY_RGMII_CLK_STABLE (0x1<<10)
  308. #define PHY_CLSA (0x1<<1)
  309. /* Configure and enable MV88E3018 PHY */
  310. void reset_phy(void)
  311. {
  312. char *name = "egiga0";
  313. unsigned short reg;
  314. if (miiphy_set_current_dev(name))
  315. return;
  316. /* RGMII clk transition on data stable */
  317. if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
  318. printf("Error reading PHY spec ctrl reg\n");
  319. if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
  320. reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
  321. printf("Error writing PHY spec ctrl reg\n");
  322. /* leds setup */
  323. if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
  324. PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
  325. printf("Error writing PHY LED reg\n");
  326. /* reset the phy */
  327. miiphy_reset(name, CONFIG_PHY_BASE_ADR);
  328. }
  329. #elif defined(CONFIG_KM_PIGGY4_88E6352)
  330. #include <mv88e6352.h>
  331. #if defined(CONFIG_KM_NUSA)
  332. struct mv88e_sw_reg extsw_conf[] = {
  333. /*
  334. * port 0, PIGGY4, autoneg
  335. * first the fix for the 1000Mbits Autoneg, this is from
  336. * a Marvell errata, the regs are undocumented
  337. */
  338. { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
  339. { PHY(0), PHY_STATUS, AN1000FIX },
  340. { PHY(0), PHY_PAGE, 0 },
  341. /* now the real port and phy configuration */
  342. { PORT(0), PORT_PHY, NO_SPEED_FOR },
  343. { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
  344. { PHY(0), PHY_1000_CTRL, NO_ADV },
  345. { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
  346. { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
  347. FULL_DUPLEX },
  348. /* port 1, unused */
  349. { PORT(1), PORT_CTRL, PORT_DIS },
  350. { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
  351. { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
  352. /* port 2, unused */
  353. { PORT(2), PORT_CTRL, PORT_DIS },
  354. { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
  355. { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
  356. /* port 3, unused */
  357. { PORT(3), PORT_CTRL, PORT_DIS },
  358. { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
  359. { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
  360. /* port 4, ICNEV, SerDes, SGMII */
  361. { PORT(4), PORT_STATUS, NO_PHY_DETECT },
  362. { PORT(4), PORT_PHY, SPEED_1000_FOR },
  363. { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
  364. { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
  365. { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
  366. /* port 5, CPU_RGMII */
  367. { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
  368. FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
  369. FULL_DPX_FOR | SPEED_1000_FOR },
  370. { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
  371. /* port 6, unused, this port has no phy */
  372. { PORT(6), PORT_CTRL, PORT_DIS },
  373. };
  374. #else
  375. struct mv88e_sw_reg extsw_conf[] = {};
  376. #endif
  377. void reset_phy(void)
  378. {
  379. #if defined(CONFIG_KM_MVEXTSW_ADDR)
  380. char *name = "egiga0";
  381. if (miiphy_set_current_dev(name))
  382. return;
  383. mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
  384. ARRAY_SIZE(extsw_conf));
  385. mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
  386. #endif
  387. }
  388. #else
  389. /* Configure and enable MV88E1118 PHY on the piggy*/
  390. void reset_phy(void)
  391. {
  392. unsigned int oui;
  393. unsigned char model, rev;
  394. char *name = "egiga0";
  395. if (miiphy_set_current_dev(name))
  396. return;
  397. /* reset the phy */
  398. miiphy_reset(name, CONFIG_PHY_BASE_ADR);
  399. /* get PHY model */
  400. if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
  401. return;
  402. /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
  403. if ((oui == PHY_MARVELL_OUI) &&
  404. (model == PHY_MARVELL_88E1118R_MODEL)) {
  405. /* set page register to 3 */
  406. if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
  407. PHY_MARVELL_PAGE_REG,
  408. PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
  409. printf("Error writing PHY page reg\n");
  410. /*
  411. * leds setup as printed on PCB:
  412. * LED2 (Link): 0x0 (On Link, Off No Link)
  413. * LED1 (Activity): 0x3 (On Activity, Off No Activity)
  414. * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
  415. */
  416. if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
  417. PHY_MARVELL_88E1118R_LED_CTRL_REG,
  418. PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
  419. PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
  420. PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
  421. PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
  422. printf("Error writing PHY LED reg\n");
  423. /* set page register back to 0 */
  424. if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
  425. PHY_MARVELL_PAGE_REG,
  426. PHY_MARVELL_DEFAULT_PAGE))
  427. printf("Error writing PHY page reg\n");
  428. }
  429. }
  430. #endif
  431. #if defined(CONFIG_HUSH_INIT_VAR)
  432. int hush_init_var(void)
  433. {
  434. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  435. return 0;
  436. }
  437. #endif
  438. #if defined(CONFIG_SYS_I2C_SOFT)
  439. void set_sda(int state)
  440. {
  441. I2C_ACTIVE;
  442. I2C_SDA(state);
  443. }
  444. void set_scl(int state)
  445. {
  446. I2C_SCL(state);
  447. }
  448. int get_sda(void)
  449. {
  450. I2C_TRISTATE;
  451. return I2C_READ;
  452. }
  453. int get_scl(void)
  454. {
  455. return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
  456. }
  457. #endif
  458. #if defined(CONFIG_POST)
  459. #define KM_POST_EN_L 44
  460. #define POST_WORD_OFF 8
  461. int post_hotkeys_pressed(void)
  462. {
  463. #if defined(CONFIG_KM_COGE5UN)
  464. return kw_gpio_get_value(KM_POST_EN_L);
  465. #else
  466. return !kw_gpio_get_value(KM_POST_EN_L);
  467. #endif
  468. }
  469. ulong post_word_load(void)
  470. {
  471. void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
  472. return in_le32(addr);
  473. }
  474. void post_word_store(ulong value)
  475. {
  476. void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
  477. out_le32(addr, value);
  478. }
  479. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  480. {
  481. *vstart = CONFIG_SYS_SDRAM_BASE;
  482. /* we go up to relocation plus a 1 MB margin */
  483. *size = CONFIG_SYS_TEXT_BASE - (1<<20);
  484. return 0;
  485. }
  486. #endif
  487. #if defined(CONFIG_SYS_EEPROM_WREN)
  488. int eeprom_write_enable(unsigned dev_addr, int state)
  489. {
  490. kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
  491. return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
  492. }
  493. #endif