igep00x0.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * ISEE 2007 SL, <www.iseebcn.com>
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <status_led.h>
  9. #include <dm.h>
  10. #include <ns16550.h>
  11. #include <twl4030.h>
  12. #include <netdev.h>
  13. #include <spl.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/mem.h>
  17. #include <asm/arch/mmc_host_def.h>
  18. #include <asm/arch/mux.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <linux/mtd/mtd.h>
  21. #include <linux/mtd/rawnand.h>
  22. #include <linux/mtd/onenand.h>
  23. #include <jffs2/load_kernel.h>
  24. #include <mtd_node.h>
  25. #include <fdt_support.h>
  26. #include "igep00x0.h"
  27. static const struct ns16550_platdata igep_serial = {
  28. .base = OMAP34XX_UART3,
  29. .reg_shift = 2,
  30. .clock = V_NS16550_CLK,
  31. .fcr = UART_FCR_DEFVAL,
  32. };
  33. U_BOOT_DEVICE(igep_uart) = {
  34. "ns16550_serial",
  35. &igep_serial
  36. };
  37. /*
  38. * Routine: get_board_revision
  39. * Description: GPIO_28 and GPIO_129 are used to read board and revision from
  40. * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from
  41. * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because
  42. * this functionality is shared by USB HOST.
  43. * Once USB reset is applied, U-boot configures these pins as input pullup to
  44. * detect board and revision:
  45. * IGEP0020-RF = 0b00
  46. * IGEP0020-RC = 0b01
  47. * IGEP0030-RG = 0b10
  48. * IGEP0030-RE = 0b11
  49. */
  50. static int get_board_revision(void)
  51. {
  52. int revision;
  53. gpio_request(IGEP0030_USB_TRANSCEIVER_RESET,
  54. "igep0030_usb_transceiver_reset");
  55. gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0);
  56. gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection");
  57. gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION);
  58. revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION);
  59. gpio_free(GPIO_IGEP00X0_BOARD_DETECTION);
  60. gpio_request(GPIO_IGEP00X0_REVISION_DETECTION,
  61. "igep00x0_revision_detection");
  62. gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION);
  63. revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION);
  64. gpio_free(GPIO_IGEP00X0_REVISION_DETECTION);
  65. gpio_free(IGEP0030_USB_TRANSCEIVER_RESET);
  66. return revision;
  67. }
  68. int onenand_board_init(struct mtd_info *mtd)
  69. {
  70. if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
  71. struct onenand_chip *this = mtd->priv;
  72. this->base = (void *)CONFIG_SYS_ONENAND_BASE;
  73. return 0;
  74. }
  75. return 1;
  76. }
  77. #if defined(CONFIG_CMD_NET)
  78. static void reset_net_chip(int gpio)
  79. {
  80. if (!gpio_request(gpio, "eth nrst")) {
  81. gpio_direction_output(gpio, 1);
  82. udelay(1);
  83. gpio_set_value(gpio, 0);
  84. udelay(40);
  85. gpio_set_value(gpio, 1);
  86. mdelay(10);
  87. }
  88. }
  89. /*
  90. * Routine: setup_net_chip
  91. * Description: Setting up the configuration GPMC registers specific to the
  92. * Ethernet hardware.
  93. */
  94. static void setup_net_chip(void)
  95. {
  96. struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  97. static const u32 gpmc_lan_config[] = {
  98. NET_LAN9221_GPMC_CONFIG1,
  99. NET_LAN9221_GPMC_CONFIG2,
  100. NET_LAN9221_GPMC_CONFIG3,
  101. NET_LAN9221_GPMC_CONFIG4,
  102. NET_LAN9221_GPMC_CONFIG5,
  103. NET_LAN9221_GPMC_CONFIG6,
  104. };
  105. enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
  106. CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
  107. /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
  108. writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
  109. /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
  110. writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
  111. /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
  112. writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
  113. &ctrl_base->gpmc_nadv_ale);
  114. reset_net_chip(64);
  115. }
  116. int board_eth_init(bd_t *bis)
  117. {
  118. #ifdef CONFIG_SMC911X
  119. return smc911x_initialize(0, CONFIG_SMC911X_BASE);
  120. #else
  121. return 0;
  122. #endif
  123. }
  124. #else
  125. static inline void setup_net_chip(void) {}
  126. #endif
  127. #ifdef CONFIG_OF_BOARD_SETUP
  128. static int ft_enable_by_compatible(void *blob, char *compat, int enable)
  129. {
  130. int off = fdt_node_offset_by_compatible(blob, -1, compat);
  131. if (off < 0)
  132. return off;
  133. if (enable)
  134. fdt_status_okay(blob, off);
  135. else
  136. fdt_status_disabled(blob, off);
  137. return 0;
  138. }
  139. int ft_board_setup(void *blob, bd_t *bd)
  140. {
  141. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  142. static const struct node_info nodes[] = {
  143. { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
  144. { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
  145. };
  146. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  147. #endif
  148. ft_enable_by_compatible(blob, "ti,omap2-nand",
  149. gpmc_cs0_flash == MTD_DEV_TYPE_NAND);
  150. ft_enable_by_compatible(blob, "ti,omap2-onenand",
  151. gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND);
  152. return 0;
  153. }
  154. #endif
  155. void set_led(void)
  156. {
  157. switch (get_board_revision()) {
  158. case 0:
  159. case 1:
  160. gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led");
  161. gpio_direction_output(IGEP0020_GPIO_LED, 1);
  162. break;
  163. case 2:
  164. case 3:
  165. gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led");
  166. gpio_direction_output(IGEP0030_GPIO_LED, 0);
  167. break;
  168. default:
  169. /* Should not happen... */
  170. break;
  171. }
  172. }
  173. void set_boardname(void)
  174. {
  175. char rev[5] = { 'F','C','G','E', };
  176. int i = get_board_revision();
  177. rev[i+1] = 0;
  178. env_set("board_rev", rev + i);
  179. env_set("board_name", i < 2 ? "igep0020" : "igep0030");
  180. }
  181. /*
  182. * Routine: misc_init_r
  183. * Description: Configure board specific parts
  184. */
  185. int misc_init_r(void)
  186. {
  187. t2_t *t2_base = (t2_t *)T2_BASE;
  188. u32 pbias_lite;
  189. twl4030_power_init();
  190. /* set VSIM to 1.8V */
  191. twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
  192. TWL4030_PM_RECEIVER_VSIM_VSEL_18,
  193. TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
  194. TWL4030_PM_RECEIVER_DEV_GRP_P1);
  195. /* set up dual-voltage GPIOs to 1.8V */
  196. pbias_lite = readl(&t2_base->pbias_lite);
  197. pbias_lite &= ~PBIASLITEVMODE1;
  198. pbias_lite |= PBIASLITEPWRDNZ1;
  199. writel(pbias_lite, &t2_base->pbias_lite);
  200. if (get_cpu_family() == CPU_OMAP36XX)
  201. writel(readl(OMAP34XX_CTRL_WKUP_CTRL) |
  202. OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
  203. OMAP34XX_CTRL_WKUP_CTRL);
  204. setup_net_chip();
  205. omap_die_id_display();
  206. set_led();
  207. set_boardname();
  208. return 0;
  209. }
  210. void board_mtdparts_default(const char **mtdids, const char **mtdparts)
  211. {
  212. struct mtd_info *mtd = get_mtd_device(NULL, 0);
  213. if (mtd) {
  214. static char ids[24];
  215. static char parts[48];
  216. const char *linux_name = "omap2-nand";
  217. if (strncmp(mtd->name, "onenand0", 8) == 0)
  218. linux_name = "omap2-onenand";
  219. snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
  220. snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
  221. linux_name, 4 * mtd->erasesize >> 10);
  222. *mtdids = ids;
  223. *mtdparts = parts;
  224. }
  225. }