mx53ppd.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 General Electric Company
  4. *
  5. * Based on board/freescale/mx53loco/mx53loco.c:
  6. *
  7. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  8. * Jason Liu <r64343@freescale.com>
  9. */
  10. #include <common.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/arch/crm_regs.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/iomux-mx53.h>
  17. #include <asm/arch/clock.h>
  18. #include <env.h>
  19. #include <linux/errno.h>
  20. #include <linux/libfdt.h>
  21. #include <asm/mach-imx/mxc_i2c.h>
  22. #include <asm/mach-imx/mx5_video.h>
  23. #include <environment.h>
  24. #include <netdev.h>
  25. #include <i2c.h>
  26. #include <mmc.h>
  27. #include <fsl_esdhc_imx.h>
  28. #include <asm/gpio.h>
  29. #include <power/pmic.h>
  30. #include <dialog_pmic.h>
  31. #include <fsl_pmic.h>
  32. #include <linux/fb.h>
  33. #include <ipu_pixfmt.h>
  34. #include <version.h>
  35. #include <watchdog.h>
  36. #include "ppd_gpio.h"
  37. #include <stdlib.h>
  38. #include "../../ge/common/ge_common.h"
  39. #include "../../ge/common/vpd_reader.h"
  40. #define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
  41. DECLARE_GLOBAL_DATA_PTR;
  42. static u32 mx53_dram_size[2];
  43. phys_size_t get_effective_memsize(void)
  44. {
  45. /*
  46. * WARNING: We must override get_effective_memsize() function here
  47. * to report only the size of the first DRAM bank. This is to make
  48. * U-Boot relocator place U-Boot into valid memory, that is, at the
  49. * end of the first DRAM bank. If we did not override this function
  50. * like so, U-Boot would be placed at the address of the first DRAM
  51. * bank + total DRAM size - sizeof(uboot), which in the setup where
  52. * each DRAM bank contains 512MiB of DRAM would result in placing
  53. * U-Boot into invalid memory area close to the end of the first
  54. * DRAM bank.
  55. */
  56. return mx53_dram_size[0];
  57. }
  58. int dram_init(void)
  59. {
  60. mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  61. mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  62. gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  63. return 0;
  64. }
  65. int dram_init_banksize(void)
  66. {
  67. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  68. gd->bd->bi_dram[0].size = mx53_dram_size[0];
  69. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  70. gd->bd->bi_dram[1].size = mx53_dram_size[1];
  71. return 0;
  72. }
  73. u32 get_board_rev(void)
  74. {
  75. return get_cpu_rev() & ~(0xF << 8);
  76. }
  77. #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  78. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  79. #ifdef CONFIG_USB_EHCI_MX5
  80. int board_ehci_hcd_init(int port)
  81. {
  82. /* request VBUS power enable pin, GPIO7_8 */
  83. imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
  84. gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
  85. return 0;
  86. }
  87. #endif
  88. static void setup_iomux_fec(void)
  89. {
  90. static const iomux_v3_cfg_t fec_pads[] = {
  91. NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  92. PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP |
  93. PAD_CTL_ODE),
  94. NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  95. NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  96. PAD_CTL_HYS | PAD_CTL_PKE),
  97. NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  98. PAD_CTL_HYS | PAD_CTL_PKE),
  99. NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
  100. NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
  101. NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  102. NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  103. PAD_CTL_HYS | PAD_CTL_PKE),
  104. NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  105. PAD_CTL_HYS | PAD_CTL_PKE),
  106. NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  107. PAD_CTL_HYS | PAD_CTL_PKE),
  108. };
  109. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  110. }
  111. #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
  112. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  113. static void setup_iomux_i2c(void)
  114. {
  115. static const iomux_v3_cfg_t i2c1_pads[] = {
  116. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
  117. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
  118. };
  119. imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
  120. }
  121. #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  122. static struct i2c_pads_info i2c_pad_info1 = {
  123. .scl = {
  124. .i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
  125. .gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD,
  126. .gp = IMX_GPIO_NR(3, 28)
  127. },
  128. .sda = {
  129. .i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
  130. .gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD,
  131. .gp = IMX_GPIO_NR(3, 21)
  132. }
  133. };
  134. static int clock_1GHz(void)
  135. {
  136. int ret;
  137. u32 ref_clk = MXC_HCLK;
  138. /*
  139. * After increasing voltage to 1.25V, we can switch
  140. * CPU clock to 1GHz and DDR to 400MHz safely
  141. */
  142. ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
  143. if (ret) {
  144. printf("CPU: Switch CPU clock to 1GHZ failed\n");
  145. return -1;
  146. }
  147. ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
  148. ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
  149. if (ret) {
  150. printf("CPU: Switch DDR clock to 400MHz failed\n");
  151. return -1;
  152. }
  153. return 0;
  154. }
  155. void ppd_gpio_init(void)
  156. {
  157. int i;
  158. imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
  159. for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i)
  160. gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
  161. }
  162. int board_early_init_f(void)
  163. {
  164. setup_iomux_fec();
  165. setup_iomux_lcd();
  166. ppd_gpio_init();
  167. return 0;
  168. }
  169. /*
  170. * Do not overwrite the console
  171. * Use always serial for U-Boot console
  172. */
  173. int overwrite_console(void)
  174. {
  175. return 1;
  176. }
  177. #define VPD_TYPE_INVALID 0x00
  178. #define VPD_BLOCK_NETWORK 0x20
  179. #define VPD_BLOCK_HWID 0x44
  180. #define VPD_PRODUCT_PPD 4
  181. #define VPD_HAS_MAC1 0x1
  182. #define VPD_MAC_ADDRESS_LENGTH 6
  183. struct vpd_cache {
  184. u8 product_id;
  185. u8 has;
  186. unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
  187. };
  188. /*
  189. * Extracts MAC and product information from the VPD.
  190. */
  191. static int vpd_callback(struct vpd_cache *userdata, u8 id, u8 version,
  192. u8 type, size_t size, u8 const *data)
  193. {
  194. struct vpd_cache *vpd = userdata;
  195. if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
  196. size >= 1) {
  197. vpd->product_id = data[0];
  198. } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
  199. type != VPD_TYPE_INVALID) {
  200. if (size >= 6) {
  201. vpd->has |= VPD_HAS_MAC1;
  202. memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
  203. }
  204. }
  205. return 0;
  206. }
  207. static void process_vpd(struct vpd_cache *vpd)
  208. {
  209. int fec_index = -1;
  210. if (vpd->product_id == VPD_PRODUCT_PPD)
  211. fec_index = 0;
  212. if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
  213. eth_env_set_enetaddr("ethaddr", vpd->mac1);
  214. }
  215. int board_init(void)
  216. {
  217. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  218. mxc_set_sata_internal_clock();
  219. setup_iomux_i2c();
  220. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  221. return 0;
  222. }
  223. int misc_init_r(void)
  224. {
  225. const char *cause;
  226. /* We care about WDOG only, treating everything else as
  227. * a power-on-reset.
  228. */
  229. if (get_imx_reset_cause() & 0x0010)
  230. cause = "WDOG";
  231. else
  232. cause = "POR";
  233. env_set("bootcause", cause);
  234. return 0;
  235. }
  236. int board_late_init(void)
  237. {
  238. int res;
  239. struct vpd_cache vpd;
  240. memset(&vpd, 0, sizeof(vpd));
  241. res = read_vpd(&vpd, vpd_callback);
  242. if (!res)
  243. process_vpd(&vpd);
  244. else
  245. printf("Can't read VPD");
  246. res = clock_1GHz();
  247. if (res != 0)
  248. return res;
  249. print_cpuinfo();
  250. hw_watchdog_init();
  251. check_time();
  252. return 0;
  253. }
  254. int checkboard(void)
  255. {
  256. puts("Board: GE PPD\n");
  257. return 0;
  258. }
  259. #ifdef CONFIG_OF_BOARD_SETUP
  260. int ft_board_setup(void *blob, bd_t *bd)
  261. {
  262. fdt_setprop(blob, 0, "ge,boot-ver", version_string,
  263. strlen(version_string) + 1);
  264. return 0;
  265. }
  266. #endif